From: Tudor Ambarus <tudor.ambarus@microchip.com>
To: <pratyush@kernel.org>, <michael@walle.cc>,
<yaliang.wang@windriver.com>, <richard@nod.at>,
<cyrille.pitchen@wedev4u.fr>, <vigneshr@ti.com>,
<andy.yan@rock-chips.com>, <miquel.raynal@bootlin.com>
Cc: Tudor Ambarus <tudor.ambarus@microchip.com>,
<linux-mtd@lists.infradead.org>, <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH v2 0/1] mtd: spi-nor: gigadevice: gd25q256: replace gd25q256_default_init with gd25q256_post_bfpt
Date: Mon, 21 Nov 2022 16:32:07 +0200 [thread overview]
Message-ID: <166904099810.93917.2481343672925708577.b4-ty@microchip.com> (raw)
In-Reply-To: <20221016171901.1483542-1-yaliang.wang@windriver.com>
On Mon, 17 Oct 2022 01:19:00 +0800, yaliang.wang@windriver.com wrote:
> GD25Q256 'C' generation 'GD25Q256C' implements the JESD216 standards,
> JESD216 doesn't define the QER field in BFPT, but the 'GD25Q256C'
> does define QE bit in status register 1 bit 6, so we need to tweak
> quad_enable to properly set the function.
>
> 'D' and 'E' generations implement the JESD216B standards, so parsing
> the SFDP to set quad_enable function is enough for them.
>
> [...]
Updated comment in gd25q256_post_bfpt and applied to spi-nor/next, thanks!
[1/1] mtd: spi-nor: gigadevice: gd25q256: replace gd25q256_default_init with gd25q256_post_bfpt
https://git.kernel.org/mtd/c/4dc49062a7e9
Best regards,
--
Tudor Ambarus <tudor.ambarus@microchip.com>
prev parent reply other threads:[~2022-11-21 14:36 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-09-13 8:40 [PATCH] " yaliang.wang
[not found] ` <MN2PR17MB3375BC0E5878B19651475413B8479@MN2PR17MB3375.namprd17.prod.outlook.com>
2022-09-14 3:05 ` Yaliang Wang
2022-09-14 7:27 ` Michael Walle
2022-10-03 5:35 ` Tudor.Ambarus
2022-10-16 8:37 ` Yaliang Wang
2022-10-16 17:19 ` [PATCH v2 0/1] " yaliang.wang
2022-10-16 17:19 ` [PATCH] " yaliang.wang
2022-11-21 14:32 ` Tudor Ambarus [this message]
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