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From: Rob Herring <robh@kernel.org>
To: Rahul Tanwar <rtanwar@maxlinear.com>
Cc: devicetree@vger.kernel.org,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
	x86@kernel.org, Borislav Petkov <bp@alien8.de>,
	Andy Shevchenko <andriy.shevchenko@linux.intel.com>,
	Marc Zyngier <maz@kernel.org>,
	linux-kernel@vger.kernel.org,
	Thomas Gleixner <tglx@linutronix.de>,
	Ingo Molnar <mingo@redhat.com>,
	Dave Hansen <dave.hansen@linux.intel.com>,
	"H. Peter Anvin" <hpa@zytor.com>,
	linux-lgm-soc@maxlinear.com, Rob Herring <robh+dt@kernel.org>
Subject: Re: [PATCH v5 2/4] dt-bindings: x86: apic: Introduce new optional bool property for lapic
Date: Wed, 30 Nov 2022 15:21:44 -0600	[thread overview]
Message-ID: <166984330418.2948681.17674473045828402706.robh@kernel.org> (raw)
In-Reply-To: <20221124084143.21841-3-rtanwar@maxlinear.com>


On Thu, 24 Nov 2022 16:41:41 +0800, Rahul Tanwar wrote:
> Intel defines a few possible interrupt delivery modes. With respect
> to boot/init time, mainly two interrupt delivery modes are possible.
> PIC Mode - Legacy external 8259 compliant PIC interrupt controller.
> Virtual Wire Mode - use lapic as virtual wire interrupt delivery mode.
> 
> For ACPI or MPS spec compliant systems, it is figured out by some read
> only bit field/s available in their respective defined data structures.
> But for OF based systems, it is by default set to PIC mode. Presently,
> it is hardcoded to legacy PIC mode for OF based x86 systems with no
> option to choose the configuration between PIC mode & virtual wire mode.
> 
> For this purpose, introduce a new boolean property for interrupt
> controller node of lapic which can allow it to be configured to virtual
> wire mode as well.
> 
> Property name: 'intel,virtual-wire-mode'
> Type: Boolean
> 
> If not present/not defined, interrupt delivery mode defaults to legacy PIC
> mode. If present/defined, interrupt delivery mode is set to virtual wire
> mode.
> 
> Suggested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
> Signed-off-by: Rahul Tanwar <rtanwar@maxlinear.com>
> ---
>  .../interrupt-controller/intel,ce4100-lapic.yaml   | 14 ++++++++++++++
>  1 file changed, 14 insertions(+)
> 

Reviewed-by: Rob Herring <robh@kernel.org>

  reply	other threads:[~2022-11-30 21:21 UTC|newest]

Thread overview: 11+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-11-24  8:41 [PATCH v5 0/4] x86/of: Add support for interrupt mode config for x86 OF systems Rahul Tanwar
2022-11-24  8:41 ` [PATCH v5 1/4] dt-bindings: x86: apic: Convert Intel's APIC bindings to YAML schema Rahul Tanwar
2022-11-30 21:21   ` Rob Herring
2022-12-02 14:04   ` [tip: x86/apic] " tip-bot2 for Rahul Tanwar
2022-11-24  8:41 ` [PATCH v5 2/4] dt-bindings: x86: apic: Introduce new optional bool property for lapic Rahul Tanwar
2022-11-30 21:21   ` Rob Herring [this message]
2022-12-02 14:03   ` [tip: x86/apic] " tip-bot2 for Rahul Tanwar
2022-11-24  8:41 ` [PATCH v5 3/4] x86/of: Replace printk(KERN_LVL) with pr_lvl() Rahul Tanwar
2022-12-02 14:03   ` [tip: x86/apic] " tip-bot2 for Rahul Tanwar
2022-11-24  8:41 ` [PATCH v5 4/4] x86/of: Add support for boot time interrupt delivery mode configuration Rahul Tanwar
2022-12-02 14:03   ` [tip: x86/apic] " tip-bot2 for Rahul Tanwar

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