From: Akhil P Oommen <akhilpo@oss.qualcomm.com>
To: Anna Maniscalco <anna.maniscalco2000@gmail.com>,
Rob Clark <robin.clark@oss.qualcomm.com>,
Sean Paul <sean@poorly.run>,
Konrad Dybcio <konradybcio@kernel.org>,
Dmitry Baryshkov <lumag@kernel.org>,
Abhinav Kumar <abhinav.kumar@linux.dev>,
Jessica Zhang <jessica.zhang@oss.qualcomm.com>,
Marijn Suijten <marijn.suijten@somainline.org>,
David Airlie <airlied@gmail.com>, Simona Vetter <simona@ffwll.ch>
Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org,
freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH 1/2] drm/msm/registers: Sync GPU registers from mesa
Date: Wed, 17 Sep 2025 20:54:56 +0530 [thread overview]
Message-ID: <16701111-9e8c-42d6-8fac-2f4b9a5e5e5d@oss.qualcomm.com> (raw)
In-Reply-To: <20250911-preemption_aware_hangcheck-v1-1-974819876819@gmail.com>
On 9/11/2025 10:31 PM, Anna Maniscalco wrote:
> In particular bring in `CP_ALWAYS_ON_CONTEXT`
>
> Signed-off-by: Anna Maniscalco <anna.maniscalco2000@gmail.com>
> ---
> drivers/gpu/drm/msm/registers/adreno/a6xx.xml | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/drivers/gpu/drm/msm/registers/adreno/a6xx.xml b/drivers/gpu/drm/msm/registers/adreno/a6xx.xml
> index 9459b603821711a1a7ed44f0f1a567cf989b749b..6ea5479670970cc610ca25e71aa41af5f328f560 100644
> --- a/drivers/gpu/drm/msm/registers/adreno/a6xx.xml
> +++ b/drivers/gpu/drm/msm/registers/adreno/a6xx.xml
> @@ -254,6 +254,7 @@ by a particular renderpass/blit.
> <bitfield name="CONTEXT" low="4" high="5"/>
> </bitset>
> <reg64 offset="0x0980" name="CP_ALWAYS_ON_COUNTER"/>
> + <reg64 offset="0x0982" name="CP_ALWAYS_ON_CONTEXT"/>
> <reg32 offset="0x098D" name="CP_AHB_CNTL"/>
> <reg32 offset="0x0A00" name="CP_APERTURE_CNTL_HOST" variants="A6XX"/>
> <reg32 offset="0x0A00" name="CP_APERTURE_CNTL_HOST" type="a7xx_aperture_cntl" variants="A7XX-"/>
>
Reviewed-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
-Akhil
next prev parent reply other threads:[~2025-09-17 15:25 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-09-11 17:01 [PATCH 0/2] Make hang check aware of preemption Anna Maniscalco
2025-09-11 17:01 ` [PATCH 1/2] drm/msm/registers: Sync GPU registers from mesa Anna Maniscalco
2025-09-17 15:24 ` Akhil P Oommen [this message]
2025-09-11 17:01 ` [PATCH 2/2] drm/msm: preemption aware hangcheck Anna Maniscalco
2025-09-17 15:23 ` Akhil P Oommen
2025-09-18 14:45 ` Anna Maniscalco
2025-09-26 21:12 ` Akhil P Oommen
2026-07-05 18:39 ` Anna Maniscalco
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