From: "tip-bot2 for Thomas Gleixner" <tip-bot2@linutronix.de>
To: linux-tip-commits@vger.kernel.org
Cc: Baoquan He <bhe@redhat.com>, Thomas Gleixner <tglx@linutronix.de>,
x86@kernel.org, linux-kernel@vger.kernel.org
Subject: [tip: x86/urgent] x86/i8259: Mark legacy PIC interrupts with IRQ_LEVEL
Date: Mon, 16 Jan 2023 16:27:49 -0000 [thread overview]
Message-ID: <167388646935.4906.13609836242653190947.tip-bot2@tip-bot2> (raw)
In-Reply-To: <87mt6rjrra.ffs@tglx>
The following commit has been merged into the x86/urgent branch of tip:
Commit-ID: 5fa55950729d0762a787451dc52862c3f850f859
Gitweb: https://git.kernel.org/tip/5fa55950729d0762a787451dc52862c3f850f859
Author: Thomas Gleixner <tglx@linutronix.de>
AuthorDate: Mon, 09 Jan 2023 22:57:13 +01:00
Committer: Thomas Gleixner <tglx@linutronix.de>
CommitterDate: Mon, 16 Jan 2023 17:24:56 +01:00
x86/i8259: Mark legacy PIC interrupts with IRQ_LEVEL
Baoquan reported that after triggering a crash the subsequent crash-kernel
fails to boot about half of the time. It triggers a NULL pointer
dereference in the periodic tick code.
This happens because the legacy timer interrupt (IRQ0) is resent in
software which happens in soft interrupt (tasklet) context. In this context
get_irq_regs() returns NULL which leads to the NULL pointer dereference.
The reason for the resend is a spurious APIC interrupt on the IRQ0 vector
which is captured and leads to a resend when the legacy timer interrupt is
enabled. This is wrong because the legacy PIC interrupts are level
triggered and therefore should never be resent in software, but nothing
ever sets the IRQ_LEVEL flag on those interrupts, so the core code does not
know about their trigger type.
Ensure that IRQ_LEVEL is set when the legacy PCI interrupts are set up.
Fixes: a4633adcdbc1 ("[PATCH] genirq: add genirq sw IRQ-retrigger")
Reported-by: Baoquan He <bhe@redhat.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Tested-by: Baoquan He <bhe@redhat.com>
Link: https://lore.kernel.org/r/87mt6rjrra.ffs@tglx
---
arch/x86/kernel/i8259.c | 1 +
arch/x86/kernel/irqinit.c | 4 +++-
2 files changed, 4 insertions(+), 1 deletion(-)
diff --git a/arch/x86/kernel/i8259.c b/arch/x86/kernel/i8259.c
index 3aa5304..4d8aff0 100644
--- a/arch/x86/kernel/i8259.c
+++ b/arch/x86/kernel/i8259.c
@@ -114,6 +114,7 @@ static void make_8259A_irq(unsigned int irq)
disable_irq_nosync(irq);
io_apic_irqs &= ~(1<<irq);
irq_set_chip_and_handler(irq, &i8259A_chip, handle_level_irq);
+ irq_set_status_flags(irq, IRQ_LEVEL);
enable_irq(irq);
lapic_assign_legacy_vector(irq, true);
}
diff --git a/arch/x86/kernel/irqinit.c b/arch/x86/kernel/irqinit.c
index beb1bad..c683666 100644
--- a/arch/x86/kernel/irqinit.c
+++ b/arch/x86/kernel/irqinit.c
@@ -65,8 +65,10 @@ void __init init_ISA_irqs(void)
legacy_pic->init(0);
- for (i = 0; i < nr_legacy_irqs(); i++)
+ for (i = 0; i < nr_legacy_irqs(); i++) {
irq_set_chip_and_handler(i, chip, handle_level_irq);
+ irq_set_status_flags(i, IRQ_LEVEL);
+ }
}
void __init init_IRQ(void)
next prev parent reply other threads:[~2023-01-16 16:39 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-12-20 5:34 [PATCH] Revert "x86/apic/x2apic: Implement IPI shorthands support" Baoquan He
2022-12-20 5:41 ` kdump kernel randomly hang with tick_periodic call trace on bare metal system Baoquan He
2022-12-20 5:51 ` Baoquan He
2022-12-21 15:46 ` Guilherme G. Piccoli
2022-12-22 4:09 ` Baoquan He
2023-01-09 21:57 ` Thomas Gleixner
2023-01-14 2:08 ` Baoquan He
2023-01-16 9:08 ` Baoquan He
2023-01-16 16:27 ` tip-bot2 for Thomas Gleixner [this message]
2022-12-20 11:38 ` [PATCH] Revert "x86/apic/x2apic: Implement IPI shorthands support" Peter Zijlstra
2022-12-20 12:38 ` Baoquan He
2023-01-04 15:18 ` Dr. David Alan Gilbert
2023-01-09 21:59 ` Thomas Gleixner
2023-01-10 2:24 ` Baoquan He
2023-01-17 8:27 ` Baoquan He
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