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[66.90.144.107]) by smtp.gmail.com with ESMTPSA id d11-20020a9d5e0b000000b006a3170fe3efsm2942956oti.27.2023.04.03.14.40.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 03 Apr 2023 14:40:23 -0700 (PDT) Received: (nullmailer pid 1920507 invoked by uid 1000); Mon, 03 Apr 2023 21:40:22 -0000 Date: Mon, 3 Apr 2023 16:40:22 -0500 From: Rob Herring To: Conor Dooley Cc: Konrad Dybcio , Paul Walmsley , Christophe Leroy , Rishabh Bhatnagar , Krzysztof Kozlowski , linux-arm-kernel@lists.infradead.org, Kunihiko Hayashi , Rob Herring , Conor Dooley , Masahiro Yamada , Masami Hiramatsu , linuxppc-dev@lists.ozlabs.org, Serge Semin , Prakash Ranjan , Palmer Dabbelt , Nicholas Piggin , linux-kernel@vger.kernel.org, Bjorn Andersson , Scott Wood , linux-arm-msm@vger.kernel.org, Andy Gross , Michael Ellerman , devicetree@vger.kernel.org, linux-riscv@lists.infradead.org Subject: Re: [PATCH v1] dt-bindings: move cache controller bindings to a cache directory Message-ID: <168055794093.1918674.10704326537545829066.robh@kernel.org> References: <20230330173255.109731-1-conor@kernel.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20230330173255.109731-1-conor@kernel.org> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, 30 Mar 2023 18:32:56 +0100, Conor Dooley wrote: > From: Conor Dooley > > There's a bunch of bindings for (mostly l2) cache controllers > scattered to the four winds, move them to a common directory. > I renamed the freescale l2cache.txt file, as while that might make sense > when the parent dir is fsl, it's confusing after the move. > The two Marvell bindings have had a "marvell," prefix added to match > their compatibles. > > Signed-off-by: Conor Dooley > --- > .../{memory-controllers => cache}/baikal,bt1-l2-ctl.yaml | 2 +- > .../{powerpc/fsl/l2cache.txt => cache/freescale-l2cache.txt} | 0 > Documentation/devicetree/bindings/{arm => cache}/l2c2x0.yaml | 2 +- > .../{arm/mrvl/feroceon.txt => cache/marvell,feroceon-cache.txt} | 0 > .../{arm/mrvl/tauros2.txt => cache/marvell,tauros2-cache.txt} | 0 > .../devicetree/bindings/{arm/msm => cache}/qcom,llcc.yaml | 2 +- > .../devicetree/bindings/{riscv => cache}/sifive,ccache0.yaml | 2 +- > .../socionext => cache}/socionext,uniphier-system-cache.yaml | 2 +- > MAINTAINERS | 2 ++ > 9 files changed, 7 insertions(+), 5 deletions(-) > rename Documentation/devicetree/bindings/{memory-controllers => cache}/baikal,bt1-l2-ctl.yaml (95%) > rename Documentation/devicetree/bindings/{powerpc/fsl/l2cache.txt => cache/freescale-l2cache.txt} (100%) > rename Documentation/devicetree/bindings/{arm => cache}/l2c2x0.yaml (99%) > rename Documentation/devicetree/bindings/{arm/mrvl/feroceon.txt => cache/marvell,feroceon-cache.txt} (100%) > rename Documentation/devicetree/bindings/{arm/mrvl/tauros2.txt => cache/marvell,tauros2-cache.txt} (100%) > rename Documentation/devicetree/bindings/{arm/msm => cache}/qcom,llcc.yaml (96%) > rename Documentation/devicetree/bindings/{riscv => cache}/sifive,ccache0.yaml (98%) > rename Documentation/devicetree/bindings/{arm/socionext => cache}/socionext,uniphier-system-cache.yaml (96%) > Applied, thanks!