From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 82F58C77B61 for ; Sat, 8 Apr 2023 10:49:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230285AbjDHKt1 (ORCPT ); Sat, 8 Apr 2023 06:49:27 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50440 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230095AbjDHKsy (ORCPT ); Sat, 8 Apr 2023 06:48:54 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 82F9DE1AB for ; Sat, 8 Apr 2023 03:48:16 -0700 (PDT) Date: Sat, 08 Apr 2023 10:45:17 -0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1680950718; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=rlXM2oUJ+UDGCP6iYnQRbV/QcA072fozjL9IZh3YPHU=; b=0vCUWkE2jE1ZER98A9UEASokEbboYrEaOcg+xSgiHO3mNJKOUWnU0dtD9LyR4wwVUv1P0F IY6vSWqO7cnUhQYDOvYSLcB3tqmyBVUtYPML6UiQzNzr1VM/whzvLoMLtAa6ITsTo8gAGf vEj8liOa4trcZvoK4DOrAe8Dog4gaOVCqCkk4Kumjd1yzmNVd5qtHgpP1XjBe3kWSDzdMZ BOajo6GBhVxdYPEEOWG82D7Wd0vOBkoKea0+pRI6PFZDLQmybO9c+p/6ZC7FUcGeO6H2gs dGhfubAKRNQ5KVgZSehfAewX2nRb5j8s84dREPCyjeKzdKdMvFP9jmzw9s241A== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1680950718; h=from:from:sender:sender:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=rlXM2oUJ+UDGCP6iYnQRbV/QcA072fozjL9IZh3YPHU=; b=OjUJizKP2j80uZRrGkPDKvGwFuj15b0Hfhzun6nWrVUJw4rB9EE9hRUyvxrJtxnd32UyZ7 RMLPCd8VrVQ3bRDg== From: "irqchip-bot for Anup Patel" Sender: tip-bot2@linutronix.de Reply-to: linux-kernel@vger.kernel.org To: linux-kernel@vger.kernel.org Subject: [irqchip: irq/irqchip-next] RISC-V: Allow marking IPIs as suitable for remote FENCEs Cc: Anup Patel , Atish Patra , Palmer Dabbelt , Marc Zyngier , tglx@linutronix.de In-Reply-To: <20230328035223.1480939-5-apatel@ventanamicro.com> References: <20230328035223.1480939-5-apatel@ventanamicro.com> MIME-Version: 1.0 Message-ID: <168095071786.404.9640710405026668539.tip-bot2@tip-bot2> Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The following commit has been merged into the irq/irqchip-next branch of irqchip: Commit-ID: fb0f3d281b7f81a11e210783940f3798c4744179 Gitweb: https://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms/fb0f3d281b7f81a11e210783940f3798c4744179 Author: Anup Patel AuthorDate: Tue, 28 Mar 2023 09:22:20 +05:30 Committer: Marc Zyngier CommitterDate: Sat, 08 Apr 2023 11:26:24 +01:00 RISC-V: Allow marking IPIs as suitable for remote FENCEs To do remote FENCEs (i.e. remote TLB flushes) using IPI calls on the RISC-V kernel, we need hardware mechanism to directly inject IPI from the supervisor mode (i.e. RISC-V kernel) instead of using SBI calls. The upcoming AIA IMSIC devices allow direct IPI injection from the supervisor mode (i.e. RISC-V kernel). To support this, we extend the riscv_ipi_set_virq_range() function so that IPI provider (i.e. irqchip drivers can mark IPIs as suitable for remote FENCEs. Signed-off-by: Anup Patel Reviewed-by: Atish Patra Acked-by: Palmer Dabbelt Signed-off-by: Marc Zyngier Link: https://lore.kernel.org/r/20230328035223.1480939-5-apatel@ventanamicro.com --- arch/riscv/include/asm/smp.h | 18 ++++++++++++++++-- arch/riscv/kernel/sbi-ipi.c | 2 +- arch/riscv/kernel/smp.c | 11 ++++++++++- drivers/clocksource/timer-clint.c | 2 +- 4 files changed, 28 insertions(+), 5 deletions(-) diff --git a/arch/riscv/include/asm/smp.h b/arch/riscv/include/asm/smp.h index 4fe7a88..c4b7701 100644 --- a/arch/riscv/include/asm/smp.h +++ b/arch/riscv/include/asm/smp.h @@ -16,6 +16,9 @@ struct seq_file; extern unsigned long boot_cpu_hartid; #ifdef CONFIG_SMP + +#include + /* * Mapping between linux logical cpu index and hartid. */ @@ -46,7 +49,12 @@ void riscv_ipi_disable(void); bool riscv_ipi_have_virq_range(void); /* Set the IPI interrupt numbers for arch (called by irqchip drivers) */ -void riscv_ipi_set_virq_range(int virq, int nr); +void riscv_ipi_set_virq_range(int virq, int nr, bool use_for_rfence); + +/* Check if we can use IPIs for remote FENCEs */ +DECLARE_STATIC_KEY_FALSE(riscv_ipi_for_rfence); +#define riscv_use_ipi_for_rfence() \ + static_branch_unlikely(&riscv_ipi_for_rfence) /* Check other CPUs stop or not */ bool smp_crash_stop_failed(void); @@ -96,10 +104,16 @@ static inline bool riscv_ipi_have_virq_range(void) return false; } -static inline void riscv_ipi_set_virq_range(int virq, int nr) +static inline void riscv_ipi_set_virq_range(int virq, int nr, + bool use_for_rfence) { } +static inline bool riscv_use_ipi_for_rfence(void) +{ + return false; +} + #endif /* CONFIG_SMP */ #if defined(CONFIG_HOTPLUG_CPU) && (CONFIG_SMP) diff --git a/arch/riscv/kernel/sbi-ipi.c b/arch/riscv/kernel/sbi-ipi.c index 41981ab..a455969 100644 --- a/arch/riscv/kernel/sbi-ipi.c +++ b/arch/riscv/kernel/sbi-ipi.c @@ -72,6 +72,6 @@ void __init sbi_ipi_init(void) "irqchip/sbi-ipi:starting", sbi_ipi_starting_cpu, NULL); - riscv_ipi_set_virq_range(virq, BITS_PER_BYTE); + riscv_ipi_set_virq_range(virq, BITS_PER_BYTE, false); pr_info("providing IPIs using SBI IPI extension\n"); } diff --git a/arch/riscv/kernel/smp.c b/arch/riscv/kernel/smp.c index 47e7ecf..5f985a1 100644 --- a/arch/riscv/kernel/smp.c +++ b/arch/riscv/kernel/smp.c @@ -177,7 +177,10 @@ bool riscv_ipi_have_virq_range(void) return (ipi_virq_base) ? true : false; } -void riscv_ipi_set_virq_range(int virq, int nr) +DEFINE_STATIC_KEY_FALSE(riscv_ipi_for_rfence); +EXPORT_SYMBOL_GPL(riscv_ipi_for_rfence); + +void riscv_ipi_set_virq_range(int virq, int nr, bool use_for_rfence) { int i, err; @@ -200,6 +203,12 @@ void riscv_ipi_set_virq_range(int virq, int nr) /* Enabled IPIs for boot CPU immediately */ riscv_ipi_enable(); + + /* Update RFENCE static key */ + if (use_for_rfence) + static_branch_enable(&riscv_ipi_for_rfence); + else + static_branch_disable(&riscv_ipi_for_rfence); } static const char * const ipi_names[] = { diff --git a/drivers/clocksource/timer-clint.c b/drivers/clocksource/timer-clint.c index 7ccc16d..9a55e73 100644 --- a/drivers/clocksource/timer-clint.c +++ b/drivers/clocksource/timer-clint.c @@ -251,7 +251,7 @@ static int __init clint_timer_init_dt(struct device_node *np) } irq_set_chained_handler(clint_ipi_irq, clint_ipi_interrupt); - riscv_ipi_set_virq_range(rc, BITS_PER_BYTE); + riscv_ipi_set_virq_range(rc, BITS_PER_BYTE, true); clint_clear_ipi(); #endif