From: "tip-bot2 for Stephane Eranian" <tip-bot2@linutronix.de>
To: linux-tip-commits@vger.kernel.org
Cc: Stephane Eranian <eranian@google.com>,
"Peter Zijlstra (Intel)" <peterz@infradead.org>,
Kan Liang <kan.liang@linux.intel.com>,
x86@kernel.org, linux-kernel@vger.kernel.org
Subject: [tip: perf/core] perf/x86/intel/uncore: Add events for Intel SPR IMC PMU
Date: Sat, 22 Apr 2023 07:50:42 -0000 [thread overview]
Message-ID: <168214984206.404.825013264888504546.tip-bot2@tip-bot2> (raw)
In-Reply-To: <20230419214241.2310385-1-eranian@google.com>
The following commit has been merged into the perf/core branch of tip:
Commit-ID: 743767d6f6b8f28228be181fe369657f7ecd1eb2
Gitweb: https://git.kernel.org/tip/743767d6f6b8f28228be181fe369657f7ecd1eb2
Author: Stephane Eranian <eranian@google.com>
AuthorDate: Wed, 19 Apr 2023 14:42:41 -07:00
Committer: Peter Zijlstra <peterz@infradead.org>
CommitterDate: Fri, 21 Apr 2023 13:24:23 +02:00
perf/x86/intel/uncore: Add events for Intel SPR IMC PMU
Add missing clockticks and cas_count_* events for Intel SapphireRapids IMC
PMU. These events are useful to measure memory bandwidth.
Signed-off-by: Stephane Eranian <eranian@google.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Reviewed-by: Kan Liang <kan.liang@linux.intel.com>
Link: https://lore.kernel.org/r/20230419214241.2310385-1-eranian@google.com
---
arch/x86/events/intel/uncore_snbep.c | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/arch/x86/events/intel/uncore_snbep.c b/arch/x86/events/intel/uncore_snbep.c
index 7d11995..fa9b209 100644
--- a/arch/x86/events/intel/uncore_snbep.c
+++ b/arch/x86/events/intel/uncore_snbep.c
@@ -6068,6 +6068,17 @@ static struct intel_uncore_ops spr_uncore_mmio_ops = {
.read_counter = uncore_mmio_read_counter,
};
+static struct uncore_event_desc spr_uncore_imc_events[] = {
+ INTEL_UNCORE_EVENT_DESC(clockticks, "event=0x01,umask=0x00"),
+ INTEL_UNCORE_EVENT_DESC(cas_count_read, "event=0x05,umask=0xcf"),
+ INTEL_UNCORE_EVENT_DESC(cas_count_read.scale, "6.103515625e-5"),
+ INTEL_UNCORE_EVENT_DESC(cas_count_read.unit, "MiB"),
+ INTEL_UNCORE_EVENT_DESC(cas_count_write, "event=0x05,umask=0xf0"),
+ INTEL_UNCORE_EVENT_DESC(cas_count_write.scale, "6.103515625e-5"),
+ INTEL_UNCORE_EVENT_DESC(cas_count_write.unit, "MiB"),
+ { /* end: all zeroes */ },
+};
+
static struct intel_uncore_type spr_uncore_imc = {
SPR_UNCORE_COMMON_FORMAT(),
.name = "imc",
@@ -6075,6 +6086,7 @@ static struct intel_uncore_type spr_uncore_imc = {
.fixed_ctr = SNR_IMC_MMIO_PMON_FIXED_CTR,
.fixed_ctl = SNR_IMC_MMIO_PMON_FIXED_CTL,
.ops = &spr_uncore_mmio_ops,
+ .event_descs = spr_uncore_imc_events,
};
static void spr_uncore_pci_enable_event(struct intel_uncore_box *box,
prev parent reply other threads:[~2023-04-22 7:50 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-04-19 21:42 [PATCH] perf/x86/intel/uncore: add " Stephane Eranian
2023-04-20 13:03 ` Liang, Kan
2023-04-22 7:50 ` tip-bot2 for Stephane Eranian [this message]
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