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([2a01:e0a:982:cbb0:765d:64ff:5f38:550]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-42ba63ae05bsm19636775e9.27.2024.08.28.05.22.38 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 28 Aug 2024 05:22:38 -0700 (PDT) Message-ID: <1684855f-5901-459a-beb7-2569003b30ac@linaro.org> Date: Wed, 28 Aug 2024 14:22:37 +0200 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird From: Neil Armstrong Reply-To: neil.armstrong@linaro.org Subject: Re: [PATCH v2 2/2] clk: qcom: gcc-sm8550: Don't use shared clk_ops for QUPs To: Stephen Boyd , Konrad Dybcio , Bjorn Andersson , Stephen Boyd Cc: linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, patches@lists.linux.dev, linux-clk@vger.kernel.org, Taniya Das , Amit Pundir References: <20240827231237.1014813-1-swboyd@chromium.org> <20240827231237.1014813-3-swboyd@chromium.org> Content-Language: en-US, fr Autocrypt: addr=neil.armstrong@linaro.org; keydata= xsBNBE1ZBs8BCAD78xVLsXPwV/2qQx2FaO/7mhWL0Qodw8UcQJnkrWmgTFRobtTWxuRx8WWP GTjuhvbleoQ5Cxjr+v+1ARGCH46MxFP5DwauzPekwJUD5QKZlaw/bURTLmS2id5wWi3lqVH4 BVF2WzvGyyeV1o4RTCYDnZ9VLLylJ9bneEaIs/7cjCEbipGGFlfIML3sfqnIvMAxIMZrvcl9 qPV2k+KQ7q+aXavU5W+yLNn7QtXUB530Zlk/d2ETgzQ5FLYYnUDAaRl+8JUTjc0CNOTpCeik 80TZcE6f8M76Xa6yU8VcNko94Ck7iB4vj70q76P/J7kt98hklrr85/3NU3oti3nrIHmHABEB AAHNKk5laWwgQXJtc3Ryb25nIDxuZWlsLmFybXN0cm9uZ0BsaW5hcm8ub3JnPsLAkQQTAQoA OwIbIwULCQgHAwUVCgkICwUWAgMBAAIeAQIXgBYhBInsPQWERiF0UPIoSBaat7Gkz/iuBQJk Q5wSAhkBAAoJEBaat7Gkz/iuyhMIANiD94qDtUTJRfEW6GwXmtKWwl/mvqQtaTtZID2dos04 YqBbshiJbejgVJjy+HODcNUIKBB3PSLaln4ltdsV73SBcwUNdzebfKspAQunCM22Mn6FBIxQ GizsMLcP/0FX4en9NaKGfK6ZdKK6kN1GR9YffMJd2P08EO8mHowmSRe/ExAODhAs9W7XXExw UNCY4pVJyRPpEhv373vvff60bHxc1k/FF9WaPscMt7hlkbFLUs85kHtQAmr8pV5Hy9ezsSRa GzJmiVclkPc2BY592IGBXRDQ38urXeM4nfhhvqA50b/nAEXc6FzqgXqDkEIwR66/Gbp0t3+r yQzpKRyQif3OwE0ETVkGzwEIALyKDN/OGURaHBVzwjgYq+ZtifvekdrSNl8TIDH8g1xicBYp QTbPn6bbSZbdvfeQPNCcD4/EhXZuhQXMcoJsQQQnO4vwVULmPGgtGf8PVc7dxKOeta+qUh6+ SRh3vIcAUFHDT3f/Zdspz+e2E0hPV2hiSvICLk11qO6cyJE13zeNFoeY3ggrKY+IzbFomIZY 4yG6xI99NIPEVE9lNBXBKIlewIyVlkOaYvJWSV+p5gdJXOvScNN1epm5YHmf9aE2ZjnqZGoM Mtsyw18YoX9BqMFInxqYQQ3j/HpVgTSvmo5ea5qQDDUaCsaTf8UeDcwYOtgI8iL4oHcsGtUX oUk33HEAEQEAAcLAXwQYAQIACQUCTVkGzwIbDAAKCRAWmrexpM/4rrXiB/sGbkQ6itMrAIfn M7IbRuiSZS1unlySUVYu3SD6YBYnNi3G5EpbwfBNuT3H8//rVvtOFK4OD8cRYkxXRQmTvqa3 3eDIHu/zr1HMKErm+2SD6PO9umRef8V82o2oaCLvf4WeIssFjwB0b6a12opuRP7yo3E3gTCS KmbUuLv1CtxKQF+fUV1cVaTPMyT25Od+RC1K+iOR0F54oUJvJeq7fUzbn/KdlhA8XPGzwGRy 4zcsPWvwnXgfe5tk680fEKZVwOZKIEuJC3v+/yZpQzDvGYJvbyix0lHnrCzq43WefRHI5XTT QbM0WUIBIcGmq38+OgUsMYu4NzLu7uZFAcmp6h8g Organization: Linaro In-Reply-To: <20240827231237.1014813-3-swboyd@chromium.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 28/08/2024 01:12, Stephen Boyd wrote: > The QUPs aren't shared in a way that requires parking the RCG at an > always on parent in case some other entity turns on the clk. The > hardware is capable of setting a new frequency itself with the DFS mode, > so parking is unnecessary. Furthermore, there aren't any GDSCs for these > devices, so there isn't a possibility of the GDSC turning on the clks > for housekeeping purposes. > > This wasn't a problem to mark these clks shared until we started parking > shared RCGs at clk registration time in commit 01a0a6cc8cfd ("clk: qcom: > Park shared RCGs upon registration"). Parking at init is actually > harmful to the UART when earlycon is used. If the device is pumping out > data while the frequency changes you'll see garbage on the serial > console until the driver can probe and actually set a proper frequency. > > Revert the QUP part of commit 929c75d57566 ("clk: qcom: gcc-sm8550: Mark > RCGs shared where applicable") so that the QUPs don't get parked during > clk registration and break UART operations. > > Fixes: 01a0a6cc8cfd ("clk: qcom: Park shared RCGs upon registration") > Fixes: 929c75d57566 ("clk: qcom: gcc-sm8550: Mark RCGs shared where applicable") > Cc: Konrad Dybcio > Cc: Bjorn Andersson > Cc: Taniya Das > Cc: Neil Armstrong > Reported-by: Amit Pundir > Closes: https://lore.kernel.org/CAMi1Hd1KQBE4kKUdAn8E5FV+BiKzuv+8FoyWQrrTHPDoYTuhgA@mail.gmail.com > Tested-by: Amit Pundir > Signed-off-by: Stephen Boyd > --- > drivers/clk/qcom/gcc-sm8550.c | 52 +++++++++++++++++------------------ > 1 file changed, 26 insertions(+), 26 deletions(-) > > diff --git a/drivers/clk/qcom/gcc-sm8550.c b/drivers/clk/qcom/gcc-sm8550.c > index 7944ddb4b47d..0244a05866b8 100644 > --- a/drivers/clk/qcom/gcc-sm8550.c > +++ b/drivers/clk/qcom/gcc-sm8550.c > @@ -536,7 +536,7 @@ static struct clk_rcg2 gcc_qupv3_i2c_s0_clk_src = { > .parent_data = gcc_parent_data_0, > .num_parents = ARRAY_SIZE(gcc_parent_data_0), > .flags = CLK_SET_RATE_PARENT, > - .ops = &clk_rcg2_shared_ops, > + .ops = &clk_rcg2_ops, > }, > }; > > @@ -551,7 +551,7 @@ static struct clk_rcg2 gcc_qupv3_i2c_s1_clk_src = { > .parent_data = gcc_parent_data_0, > .num_parents = ARRAY_SIZE(gcc_parent_data_0), > .flags = CLK_SET_RATE_PARENT, > - .ops = &clk_rcg2_shared_ops, > + .ops = &clk_rcg2_ops, > }, > }; > > @@ -566,7 +566,7 @@ static struct clk_rcg2 gcc_qupv3_i2c_s2_clk_src = { > .parent_data = gcc_parent_data_0, > .num_parents = ARRAY_SIZE(gcc_parent_data_0), > .flags = CLK_SET_RATE_PARENT, > - .ops = &clk_rcg2_shared_ops, > + .ops = &clk_rcg2_ops, > }, > }; > > @@ -581,7 +581,7 @@ static struct clk_rcg2 gcc_qupv3_i2c_s3_clk_src = { > .parent_data = gcc_parent_data_0, > .num_parents = ARRAY_SIZE(gcc_parent_data_0), > .flags = CLK_SET_RATE_PARENT, > - .ops = &clk_rcg2_shared_ops, > + .ops = &clk_rcg2_ops, > }, > }; > > @@ -596,7 +596,7 @@ static struct clk_rcg2 gcc_qupv3_i2c_s4_clk_src = { > .parent_data = gcc_parent_data_0, > .num_parents = ARRAY_SIZE(gcc_parent_data_0), > .flags = CLK_SET_RATE_PARENT, > - .ops = &clk_rcg2_shared_ops, > + .ops = &clk_rcg2_ops, > }, > }; > > @@ -611,7 +611,7 @@ static struct clk_rcg2 gcc_qupv3_i2c_s5_clk_src = { > .parent_data = gcc_parent_data_0, > .num_parents = ARRAY_SIZE(gcc_parent_data_0), > .flags = CLK_SET_RATE_PARENT, > - .ops = &clk_rcg2_shared_ops, > + .ops = &clk_rcg2_ops, > }, > }; > > @@ -626,7 +626,7 @@ static struct clk_rcg2 gcc_qupv3_i2c_s6_clk_src = { > .parent_data = gcc_parent_data_0, > .num_parents = ARRAY_SIZE(gcc_parent_data_0), > .flags = CLK_SET_RATE_PARENT, > - .ops = &clk_rcg2_shared_ops, > + .ops = &clk_rcg2_ops, > }, > }; > > @@ -641,7 +641,7 @@ static struct clk_rcg2 gcc_qupv3_i2c_s7_clk_src = { > .parent_data = gcc_parent_data_0, > .num_parents = ARRAY_SIZE(gcc_parent_data_0), > .flags = CLK_SET_RATE_PARENT, > - .ops = &clk_rcg2_shared_ops, > + .ops = &clk_rcg2_ops, > }, > }; > > @@ -656,7 +656,7 @@ static struct clk_rcg2 gcc_qupv3_i2c_s8_clk_src = { > .parent_data = gcc_parent_data_0, > .num_parents = ARRAY_SIZE(gcc_parent_data_0), > .flags = CLK_SET_RATE_PARENT, > - .ops = &clk_rcg2_shared_ops, > + .ops = &clk_rcg2_ops, > }, > }; > > @@ -671,7 +671,7 @@ static struct clk_rcg2 gcc_qupv3_i2c_s9_clk_src = { > .parent_data = gcc_parent_data_0, > .num_parents = ARRAY_SIZE(gcc_parent_data_0), > .flags = CLK_SET_RATE_PARENT, > - .ops = &clk_rcg2_shared_ops, > + .ops = &clk_rcg2_ops, > }, > }; > > @@ -700,7 +700,7 @@ static struct clk_init_data gcc_qupv3_wrap1_s0_clk_src_init = { > .parent_data = gcc_parent_data_0, > .num_parents = ARRAY_SIZE(gcc_parent_data_0), > .flags = CLK_SET_RATE_PARENT, > - .ops = &clk_rcg2_shared_ops, > + .ops = &clk_rcg2_ops, > }; > > static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = { > @@ -717,7 +717,7 @@ static struct clk_init_data gcc_qupv3_wrap1_s1_clk_src_init = { > .parent_data = gcc_parent_data_0, > .num_parents = ARRAY_SIZE(gcc_parent_data_0), > .flags = CLK_SET_RATE_PARENT, > - .ops = &clk_rcg2_shared_ops, > + .ops = &clk_rcg2_ops, > }; > > static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src = { > @@ -750,7 +750,7 @@ static struct clk_init_data gcc_qupv3_wrap1_s2_clk_src_init = { > .parent_data = gcc_parent_data_0, > .num_parents = ARRAY_SIZE(gcc_parent_data_0), > .flags = CLK_SET_RATE_PARENT, > - .ops = &clk_rcg2_shared_ops, > + .ops = &clk_rcg2_ops, > }; > > static struct clk_rcg2 gcc_qupv3_wrap1_s2_clk_src = { > @@ -767,7 +767,7 @@ static struct clk_init_data gcc_qupv3_wrap1_s3_clk_src_init = { > .parent_data = gcc_parent_data_0, > .num_parents = ARRAY_SIZE(gcc_parent_data_0), > .flags = CLK_SET_RATE_PARENT, > - .ops = &clk_rcg2_shared_ops, > + .ops = &clk_rcg2_ops, > }; > > static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src = { > @@ -784,7 +784,7 @@ static struct clk_init_data gcc_qupv3_wrap1_s4_clk_src_init = { > .parent_data = gcc_parent_data_0, > .num_parents = ARRAY_SIZE(gcc_parent_data_0), > .flags = CLK_SET_RATE_PARENT, > - .ops = &clk_rcg2_shared_ops, > + .ops = &clk_rcg2_ops, > }; > > static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src = { > @@ -801,7 +801,7 @@ static struct clk_init_data gcc_qupv3_wrap1_s5_clk_src_init = { > .parent_data = gcc_parent_data_0, > .num_parents = ARRAY_SIZE(gcc_parent_data_0), > .flags = CLK_SET_RATE_PARENT, > - .ops = &clk_rcg2_shared_ops, > + .ops = &clk_rcg2_ops, > }; > > static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src = { > @@ -818,7 +818,7 @@ static struct clk_init_data gcc_qupv3_wrap1_s6_clk_src_init = { > .parent_data = gcc_parent_data_0, > .num_parents = ARRAY_SIZE(gcc_parent_data_0), > .flags = CLK_SET_RATE_PARENT, > - .ops = &clk_rcg2_shared_ops, > + .ops = &clk_rcg2_ops, > }; > > static struct clk_rcg2 gcc_qupv3_wrap1_s6_clk_src = { > @@ -835,7 +835,7 @@ static struct clk_init_data gcc_qupv3_wrap1_s7_clk_src_init = { > .parent_data = gcc_parent_data_0, > .num_parents = ARRAY_SIZE(gcc_parent_data_0), > .flags = CLK_SET_RATE_PARENT, > - .ops = &clk_rcg2_shared_ops, > + .ops = &clk_rcg2_ops, > }; > > static struct clk_rcg2 gcc_qupv3_wrap1_s7_clk_src = { > @@ -852,7 +852,7 @@ static struct clk_init_data gcc_qupv3_wrap2_s0_clk_src_init = { > .parent_data = gcc_parent_data_0, > .num_parents = ARRAY_SIZE(gcc_parent_data_0), > .flags = CLK_SET_RATE_PARENT, > - .ops = &clk_rcg2_shared_ops, > + .ops = &clk_rcg2_ops, > }; > > static struct clk_rcg2 gcc_qupv3_wrap2_s0_clk_src = { > @@ -869,7 +869,7 @@ static struct clk_init_data gcc_qupv3_wrap2_s1_clk_src_init = { > .parent_data = gcc_parent_data_0, > .num_parents = ARRAY_SIZE(gcc_parent_data_0), > .flags = CLK_SET_RATE_PARENT, > - .ops = &clk_rcg2_shared_ops, > + .ops = &clk_rcg2_ops, > }; > > static struct clk_rcg2 gcc_qupv3_wrap2_s1_clk_src = { > @@ -886,7 +886,7 @@ static struct clk_init_data gcc_qupv3_wrap2_s2_clk_src_init = { > .parent_data = gcc_parent_data_0, > .num_parents = ARRAY_SIZE(gcc_parent_data_0), > .flags = CLK_SET_RATE_PARENT, > - .ops = &clk_rcg2_shared_ops, > + .ops = &clk_rcg2_ops, > }; > > static struct clk_rcg2 gcc_qupv3_wrap2_s2_clk_src = { > @@ -903,7 +903,7 @@ static struct clk_init_data gcc_qupv3_wrap2_s3_clk_src_init = { > .parent_data = gcc_parent_data_0, > .num_parents = ARRAY_SIZE(gcc_parent_data_0), > .flags = CLK_SET_RATE_PARENT, > - .ops = &clk_rcg2_shared_ops, > + .ops = &clk_rcg2_ops, > }; > > static struct clk_rcg2 gcc_qupv3_wrap2_s3_clk_src = { > @@ -920,7 +920,7 @@ static struct clk_init_data gcc_qupv3_wrap2_s4_clk_src_init = { > .parent_data = gcc_parent_data_0, > .num_parents = ARRAY_SIZE(gcc_parent_data_0), > .flags = CLK_SET_RATE_PARENT, > - .ops = &clk_rcg2_shared_ops, > + .ops = &clk_rcg2_ops, > }; > > static struct clk_rcg2 gcc_qupv3_wrap2_s4_clk_src = { > @@ -937,7 +937,7 @@ static struct clk_init_data gcc_qupv3_wrap2_s5_clk_src_init = { > .parent_data = gcc_parent_data_0, > .num_parents = ARRAY_SIZE(gcc_parent_data_0), > .flags = CLK_SET_RATE_PARENT, > - .ops = &clk_rcg2_shared_ops, > + .ops = &clk_rcg2_ops, > }; > > static struct clk_rcg2 gcc_qupv3_wrap2_s5_clk_src = { > @@ -975,7 +975,7 @@ static struct clk_init_data gcc_qupv3_wrap2_s6_clk_src_init = { > .parent_data = gcc_parent_data_8, > .num_parents = ARRAY_SIZE(gcc_parent_data_8), > .flags = CLK_SET_RATE_PARENT, > - .ops = &clk_rcg2_shared_ops, > + .ops = &clk_rcg2_ops, > }; > > static struct clk_rcg2 gcc_qupv3_wrap2_s6_clk_src = { > @@ -992,7 +992,7 @@ static struct clk_init_data gcc_qupv3_wrap2_s7_clk_src_init = { > .parent_data = gcc_parent_data_0, > .num_parents = ARRAY_SIZE(gcc_parent_data_0), > .flags = CLK_SET_RATE_PARENT, > - .ops = &clk_rcg2_shared_ops, > + .ops = &clk_rcg2_ops, > }; > > static struct clk_rcg2 gcc_qupv3_wrap2_s7_clk_src = { I think you missed gcc_qupv3_wrap2_s7_clk_src