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Thu, 27 Aug 2026 06:51:01 -0700 (PDT) Sender: Guenter Roeck Date: Thu, 27 Aug 2026 06:51:00 -0700 From: Guenter Roeck To: Aiden Isik Cc: Wim Van Sebroeck , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Peter Griffin , Alim Akhtar , Krzysztof Kozlowski , linux-watchdog@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org Subject: Re: [PATCH v4 2/2] watchdog: s3c2410_wdt: Add exynos5515-wdt compatible data Message-ID: <168be4ed-d670-4d61-a061-e01abb33efa4@roeck-us.net> References: <20260821-for-next-lucky7-watchdog-v4-0-d070cee5009f@member.fsf.org> <20260821-for-next-lucky7-watchdog-v4-2-d070cee5009f@member.fsf.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20260821-for-next-lucky7-watchdog-v4-2-d070cee5009f@member.fsf.org> On Fri, Aug 21, 2026 at 04:14:50PM +0100, Aiden Isik wrote: > From: Aiden Isik > > Add driver data for the Exynos5515 SoC's watchdog timer. > > Unlike similar SoCs such as GS101 or Exynos990, Exynos5515's PMU does > not require explicit counter enablement for the watchdog to tick. > > Signed-off-by: Aiden Isik > Reviewed-by: Krzysztof Kozlowski Applied. Thanks, Guenter > --- > drivers/watchdog/s3c2410_wdt.c | 16 ++++++++++++++++ > 1 file changed, 16 insertions(+) > > diff --git a/drivers/watchdog/s3c2410_wdt.c b/drivers/watchdog/s3c2410_wdt.c > index e31f93db0509..e61439a3f4b2 100644 > --- a/drivers/watchdog/s3c2410_wdt.c > +++ b/drivers/watchdog/s3c2410_wdt.c > @@ -232,6 +232,20 @@ static const struct s3c2410_wdt_variant drv_data_exynos5420 = { > QUIRK_HAS_PMU_RST_STAT | QUIRK_HAS_PMU_AUTO_DISABLE, > }; > > +/* > + * Unlike similar SoCs like GS101, Exynos5515's PMU does not require > + * explicit counter enablement. Hence, QUIRK_HAS_PMU_CNT_EN is not set. > + */ > +static const struct s3c2410_wdt_variant drv_data_exynos5515 = { > + .mask_reset_reg = EXYNOSAUTOV920_CLUSTER0_NONCPU_INT_EN, > + .mask_bit = 2, > + .mask_reset_inv = true, > + .rst_stat_reg = EXYNOS5_RST_STAT_REG_OFFSET, > + .rst_stat_bit = 24, > + .quirks = QUIRK_HAS_WTCLRINT_REG | QUIRK_HAS_PMU_MASK_RESET | \ > + QUIRK_HAS_PMU_RST_STAT | QUIRK_HAS_DBGACK_BIT, > +}; > + > static const struct s3c2410_wdt_variant drv_data_exynos7 = { > .disable_reg = EXYNOS5_WDT_DISABLE_REG_OFFSET, > .mask_reset_reg = EXYNOS5_WDT_MASK_RESET_REG_OFFSET, > @@ -379,6 +393,8 @@ static const struct of_device_id s3c2410_wdt_match[] = { > .data = &drv_data_exynos5250 }, > { .compatible = "samsung,exynos5420-wdt", > .data = &drv_data_exynos5420 }, > + { .compatible = "samsung,exynos5515-wdt", > + .data = &drv_data_exynos5515 }, > { .compatible = "samsung,exynos7-wdt", > .data = &drv_data_exynos7 }, > { .compatible = "samsung,exynos850-wdt",