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charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Proofpoint-GUID: CeHYcAa-xr1bjNUdOOYKQnJpgEp83t8- X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMzE2MDAzNiBTYWx0ZWRfX7HuxXj6vZrKr RWQAd8aZdy+q9aYhYZzRrfqyW0PBN9w0nC/dMpDOHMSuwEgNBLfeUqhiBBwBRla78Dm3fIId1Bj 8JJevq9vwP81hBIgZsv8qb9vZPOIEGuHmMdrH5IOy8Rydc2CnXAP3vYttBPdtSuvUWu9qX0gXgw Xc5jxW4NSQEbN54Ld5Kxoe43oQqEnAAHWe4NcMSgaY0Rv3zGT0b01Y2uDtm30nvyWQyH95yI4B7 RedD3gQ1vnUep1NWqUGXE18kIbr8DVPUhTnNRw5ZHbeSh9VLOiDvnXX11btxxs2REVUsVl1iFW0 DFNrgv5Yg+QKiLIu0Br+c31EdLEC+qI0tYSDYvF7GG/iXrbqPYYYllVOGDZcA4EXzml4pESYv3J AiIlrF5/y+fzpdW5q2gcqrJyjZo/w3pgw3h7/YHO8TVRiMEqf8Gp0zE5E1DQSmJlhFRbqElv01v KdxVCwXZjlWRFEU/Riw== X-Proofpoint-ORIG-GUID: CeHYcAa-xr1bjNUdOOYKQnJpgEp83t8- X-Authority-Analysis: v=2.4 cv=ZbQQ98VA c=1 sm=1 tr=0 ts=69b78fdf cx=c_pps a=JL+w9abYAAE89/QcEU+0QA==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=Yq5XynenixoA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=rJkE3RaqiGZ5pbrm-msn:22 a=EUspDBNiAAAA:8 a=0zj2Sjq5_81KAJ-Os-gA:9 a=QEXdDO2ut3YA:10 a=324X-CrmTo6CU4MGRt3R:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-03-16_02,2026-03-13_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 priorityscore=1501 adultscore=0 suspectscore=0 lowpriorityscore=0 malwarescore=0 clxscore=1015 phishscore=0 spamscore=0 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2603050001 definitions=main-2603160036 On 3/16/2026 10:21 AM, Manivannan Sadhasivam wrote: > On Wed, Mar 11, 2026 at 06:10:38PM +0530, Krishna Chaitanya Chundru wrote: >> Add a shared helper to encode the PCIe L1 PM Substates T_POWER_ON >> parameter into the T_POWER_ON_Scale and T_POWER_ON_Value fields. >> >> This helper can be used by the controller drivers to change the >> default/wrong value of T_POWER_ON in L1ss capability register to >> avoid incorrect calculation of LTR_L1.2_THRESHOLD value. >> >> The helper converts a T_POWER_ON time specified in microseconds into >> the appropriate scale/value encoding defined by the PCIe spec r7.0, >> sec 7.8.3.2. Values that exceed the maximum encodable range are clamped >> to the largest representable encoding. >> >> Signed-off-by: Krishna Chaitanya Chundru >> --- >> drivers/pci/pci.h | 2 ++ >> drivers/pci/pcie/aspm.c | 43 +++++++++++++++++++++++++++++++++++++++++++ >> 2 files changed, 45 insertions(+) >> >> diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h >> index 13d998fbacce6698514d92500dfea03cc562cdc2..48964602d802e114a6a2481df3fb75d9e178a31b 100644 >> --- a/drivers/pci/pci.h >> +++ b/drivers/pci/pci.h >> @@ -1105,6 +1105,7 @@ void pcie_aspm_pm_state_change(struct pci_dev *pdev, bool locked); >> void pcie_aspm_powersave_config_link(struct pci_dev *pdev); >> void pci_configure_ltr(struct pci_dev *pdev); >> void pci_bridge_reconfigure_ltr(struct pci_dev *pdev); >> +void pcie_encode_t_power_on(u16 t_power_on_us, u8 *scale, u8 *value); >> #else >> static inline void pcie_aspm_remove_cap(struct pci_dev *pdev, u32 lnkcap) { } >> static inline void pcie_aspm_init_link_state(struct pci_dev *pdev) { } >> @@ -1113,6 +1114,7 @@ static inline void pcie_aspm_pm_state_change(struct pci_dev *pdev, bool locked) >> static inline void pcie_aspm_powersave_config_link(struct pci_dev *pdev) { } >> static inline void pci_configure_ltr(struct pci_dev *pdev) { } >> static inline void pci_bridge_reconfigure_ltr(struct pci_dev *pdev) { } >> +static inline void pcie_encode_t_power_on(u16 t_power_on_us, u8 *scale, u8 *value) { } >> #endif >> >> #ifdef CONFIG_PCIE_ECRC >> diff --git a/drivers/pci/pcie/aspm.c b/drivers/pci/pcie/aspm.c >> index 21f5d23e0b61bd7e1163cc869fe9356d1ab87b34..d7f9ae9e48c25dbc2d9b4887e2f74623688098e0 100644 >> --- a/drivers/pci/pcie/aspm.c >> +++ b/drivers/pci/pcie/aspm.c >> @@ -525,6 +525,49 @@ static u32 calc_l12_pwron(struct pci_dev *pdev, u32 scale, u32 val) >> return 0; >> } >> >> +/** >> + * pcie_encode_t_power_on - Encode T_POWER_ON into scale and value fields >> + * @t_power_on_us: T_POWER_ON time in microseconds >> + * @scale: Encoded T_POWER_ON_Scale (0..2) >> + * @value: Encoded T_POWER_ON_Value > Nit: > > s/T_POWER_ON_Scale/T_POWER_ON Scale > s/T_POWER_ON_Value/T_POWER_ON Value > > Same everywhere. > >> + * >> + * T_POWER_ON is encoded as: >> + * T_POWER_ON(us) = scale_unit(us) * value >> + * >> + * where scale_unit is selected by @scale: >> + * 0: 2us >> + * 1: 10us >> + * 2: 100us >> + * >> + * If @t_power_on_us exceeds the maximum representable value, the result >> + * is clamped to the largest encodable T_POWER_ON. >> + * >> + * See PCIe r7.0, sec 7.8.3.2. >> + */ >> +void pcie_encode_t_power_on(u16 t_power_on_us, u8 *scale, u8 *value) >> +{ >> + u8 maxv = FIELD_MAX(PCI_L1SS_CTL2_T_PWR_ON_VALUE); > Since this API is for changing the 'capabilities register', you should use > PCI_L1SS_CAP_P_PWR_ON_VALUE. Ack. - Krishna Chaitanya. >> + /* >> + * T_POWER_ON_Value ("value") is a 5-bit field with max >> + * value of 31. > Use max 80 columns for comments. > > - Mani >