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([2600:1700:dfe0:49f0:802c:b332:26e0:e0aa]) by smtp.gmail.com with ESMTPSA id m5sm4054705qtk.88.2021.10.10.18.50.40 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sun, 10 Oct 2021 18:50:41 -0700 (PDT) Message-ID: <16d2a19b-5092-763b-230c-5b0a6237d852@gmail.com> Date: Sun, 10 Oct 2021 18:50:39 -0700 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:91.0) Gecko/20100101 Thunderbird/91.1.2 Subject: Re: [net-next PATCH v5 04/14] dt-bindings: net: dsa: qca8k: Document support for CPU port 6 Content-Language: en-US To: Ansuel Smith , Andrew Lunn , Vivien Didelot , Vladimir Oltean , "David S. Miller" , Jakub Kicinski , Rob Herring , Russell King , netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20211011013024.569-1-ansuelsmth@gmail.com> <20211011013024.569-5-ansuelsmth@gmail.com> From: Florian Fainelli In-Reply-To: <20211011013024.569-5-ansuelsmth@gmail.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 10/10/2021 6:30 PM, Ansuel Smith wrote: > The switch now support CPU port to be set 6 instead of be hardcoded to > 0. Document support for it and describe logic selection. > > Signed-off-by: Ansuel Smith > --- > Documentation/devicetree/bindings/net/dsa/qca8k.txt | 6 +++++- > 1 file changed, 5 insertions(+), 1 deletion(-) > > diff --git a/Documentation/devicetree/bindings/net/dsa/qca8k.txt b/Documentation/devicetree/bindings/net/dsa/qca8k.txt > index cc214e655442..aeb206556f54 100644 > --- a/Documentation/devicetree/bindings/net/dsa/qca8k.txt > +++ b/Documentation/devicetree/bindings/net/dsa/qca8k.txt > @@ -29,7 +29,11 @@ the mdio MASTER is used as communication. > Don't use mixed external and internal mdio-bus configurations, as this is > not supported by the hardware. > > -The CPU port of this switch is always port 0. > +This switch support 2 CPU port. Plural: ports. > Normally and advised configuration is with > +CPU port set to port 0. It is also possible to set the CPU port to port 6 > +if the device requires it. The driver will configure the switch to the defined > +port. With both CPU port declared the first CPU port is selected as primary > +and the secondary CPU ignored. Is this universally supported by all models that this binding covers? If not, you might want to explain that? -- Florian