Re: [PATCH] mailbox: mtk-cmdq: Refine GCE_GCTL_VALUE setting

["Jason-JH Lin (林睿祥)" <Jason-JH.Lin@mediatek.com>]

Hi CK,

Thanks for the reviews.

On Mon, 2025-02-24 at 06:04 +0000, CK Hu (胡俊光) wrote:
> On Mon, 2025-02-24 at 13:01 +0800, Jason-JH Lin wrote:
> > Add cmdq_gctl_value_toggle() to configure GCE_CTRL_BY_SW and
> > GCE_DDR_EN
> > together in same the GCE_GCTL_VALUE register.
> > 
> > Move this function into cmdq_runtime_resume() and
> > cmdq_runtime_suspend()
> > to ensure it can be called when the GCE clock is enabled.
> 
> Why need GCE clock to be enabled when toggle GCE_GCTL_VALUE register?

All the GCE registers should be written after GCE clocks enabled.

> In some hardware, just need power on to access register. It's not
> necessary to enable clock.

MT8196 GCE is placed in MMINFRA and using MMINFRA_AO power, so it can
be written without enabling the clocks.

> If GCE need to enable clock to access register, add information here.

OK, I'll add the description above into the commit message.

> 
> > 
> > Fixes: 7abd037aa581 ("mailbox: mtk-cmdq: add gce ddr enable support
> > flow")
> > Signed-off-by: Jason-JH Lin <jason-jh.lin@mediatek.com>
> > ---
> >  drivers/mailbox/mtk-cmdq-mailbox.c | 41 +++++++++++++-------------
> > ----
> >  1 file changed, 17 insertions(+), 24 deletions(-)
> > 
> > diff --git a/drivers/mailbox/mtk-cmdq-mailbox.c
> > b/drivers/mailbox/mtk-cmdq-mailbox.c
> > index d186865b8dce..be17697d7785 100644
> > --- a/drivers/mailbox/mtk-cmdq-mailbox.c
> > +++ b/drivers/mailbox/mtk-cmdq-mailbox.c
> > @@ -92,16 +92,17 @@ struct gce_plat {
> >  	u32 gce_num;
> >  };
> >  
> > -static void cmdq_sw_ddr_enable(struct cmdq *cmdq, bool enable)
> > +static void cmdq_gctl_value_toggle(struct cmdq *cmdq, bool
> > ddr_enable)
> >  {
> > -	WARN_ON(clk_bulk_enable(cmdq->pdata->gce_num, cmdq-
> > >clocks));
> > +	u32 val = (cmdq->pdata->control_by_sw) ? GCE_CTRL_BY_SW :
> > 0;
> 
> u32 val = cmdq->pdata->control_by_sw ? GCE_CTRL_BY_SW : 0;
> 

OK, I'll change to this.

Regards,
Jason-JH Lin