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From: Andrew Lunn <andrew@lunn.ch>
To: Thomas Gessler <thomas.gessler@brueckmann-gmbh.de>
Cc: Heiner Kallweit <hkallweit1@gmail.com>,
	Russell King <linux@armlinux.org.uk>,
	"David S. Miller" <davem@davemloft.net>,
	Eric Dumazet <edumazet@google.com>,
	Jakub Kicinski <kuba@kernel.org>, Paolo Abeni <pabeni@redhat.com>,
	netdev@vger.kernel.org, linux-kernel@vger.kernel.org,
	MD Danish Anwar <danishanwar@ti.com>,
	Ravi Gunasekaran <r-gunasekaran@ti.com>
Subject: Re: [PATCH 2/2] net: phy: dp83869: Fix RGMII-SGMII and 1000BASE-X
Date: Tue, 14 May 2024 15:08:59 +0200	[thread overview]
Message-ID: <16f79b3f-0b33-4196-858a-b1469ed1200b@lunn.ch> (raw)
In-Reply-To: <20240514122728.1490156-2-thomas.gessler@brueckmann-gmbh.de>

> +/* FX_CTRL bits */
> +#define DP83869_CTRL0_SPEED_SEL_MSB		BIT(6)
> +#define DP83869_CTRL0_DUPLEX_MODE		BIT(8)
> +#define DP83869_CTRL0_RESTART_AN		BIT(9)
> +#define DP83869_CTRL0_ISOLATE			BIT(10)
> +#define DP83869_CTRL0_PWRDN			BIT(11)
> +#define DP83869_CTRL0_ANEG_EN			BIT(12)
> +#define DP83869_CTRL0_SPEED_SEL_LSB		BIT(13)
> +#define DP83869_CTRL0_LOOPBACK			BIT(14)

This looks like a standard BMCR. Please just use defines from mii.h,
since they are well known.

> +/* FX_STS bits */
> +#define DP83869_STTS_LINK_STATUS		BIT(2)
> +#define DP83869_STTS_ANEG_COMPLETE		BIT(5)

And these are standard BMCR bits.

> +
> +/* FX_ANADV bits */
> +#define DP83869_BP_FULL_DUPLEX			BIT(5)
> +#define DP83869_BP_HALF_DUPLEX			BIT(6)
> +#define DP83869_BP_PAUSE			BIT(7)
> +#define DP83869_BP_ASYMMETRIC_PAUSE		BIT(8)

ADVERTISE_1000XPSE_ASYN, ADVERTISE_1000XPAUSE, ...

Please go through all these defines and see what match to existing
ones.

	Andrew

  parent reply	other threads:[~2024-05-14 13:09 UTC|newest]

Thread overview: 11+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-05-14 12:27 [PATCH 1/2] net: phy: dp83869: Add PHY ID for chip revision 3 Thomas Gessler
2024-05-14 12:27 ` [PATCH 2/2] net: phy: dp83869: Fix RGMII-SGMII and 1000BASE-X Thomas Gessler
2024-05-14 12:56   ` Andrew Lunn
2024-05-15  8:15     ` Thomas Geßler
2024-05-15 15:10       ` Andrew Lunn
2024-05-14 13:05   ` Russell King (Oracle)
2024-05-15  8:45     ` Thomas Geßler
2024-05-14 13:08   ` Andrew Lunn [this message]
2024-05-15  7:47     ` Thomas Geßler
2024-05-14 12:47 ` [PATCH 1/2] net: phy: dp83869: Add PHY ID for chip revision 3 Andrew Lunn
2024-05-15  7:04   ` Thomas Geßler

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