From: Can Guo <quic_cang@quicinc.com>
To: quic_cang@quicinc.com, bvanassche@acm.org, mani@kernel.org,
stanley.chu@mediatek.com, adrian.hunter@intel.com,
beanhuo@micron.com, avri.altman@wdc.com,
junwoo80.lee@samsung.com, martin.petersen@oracle.com
Cc: Andy Gross <agross@kernel.org>,
Bjorn Andersson <andersson@kernel.org>,
Konrad Dybcio <konrad.dybcio@linaro.org>,
Vinod Koul <vkoul@kernel.org>,
Kishon Vijay Abraham I <kishon@kernel.org>,
linux-arm-msm@vger.kernel.org (open list:ARM/QUALCOMM SUPPORT),
linux-phy@lists.infradead.org (open list:GENERIC PHY FRAMEWORK),
linux-kernel@vger.kernel.org (open list)
Subject: [PATCH v3 09/11] phy: qualcomm: phy-qcom-qmp-ufs: Use tbls_hs_max instead of tbls_hs_g4
Date: Tue, 21 Nov 2023 23:10:40 -0800 [thread overview]
Message-ID: <1700637042-11104-10-git-send-email-quic_cang@quicinc.com> (raw)
In-Reply-To: <1700637042-11104-1-git-send-email-quic_cang@quicinc.com>
Table tbls_hs_g4 is added to support HS Gear 4 and applied only if PHY
submode is HS_G4. In future, we are adding support for Gear 5 and higher.
To avoiding adding more tables, like tbls_hs_g5, let's use tbls_hs_max
instead of tbls_hs_g4. In addition, max_hs_gear is added to indicate the
maximum supported HS Gear of each configuration, so that we can check PHY
submode against it to tell if tbls_hs_max needs to be applied.
Signed-off-by: Can Guo <quic_cang@quicinc.com>
---
drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 49 +++++++++++++++++----------------
1 file changed, 26 insertions(+), 23 deletions(-)
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
index ad91f92..cae27a9 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
@@ -735,8 +735,11 @@ struct qmp_phy_cfg {
const struct qmp_phy_cfg_tbls tbls;
/* Additional sequence for HS Series B */
const struct qmp_phy_cfg_tbls tbls_hs_b;
- /* Additional sequence for HS G4 */
- const struct qmp_phy_cfg_tbls tbls_hs_g4;
+ /* Additional sequence for maximum supported HS Gear */
+ const struct qmp_phy_cfg_tbls tbls_hs_max;
+
+ /* Maximum supported HS Gear */
+ u32 max_hs_gear;
/* clock ids to be requested */
const char * const *clk_list;
@@ -839,7 +842,7 @@ static const struct qmp_phy_cfg msm8996_ufsphy_cfg = {
.lanes = 1,
.offsets = &qmp_ufs_offsets,
-
+ .max_hs_gear = UFS_HS_G3,
.tbls = {
.serdes = msm8996_ufsphy_serdes,
.serdes_num = ARRAY_SIZE(msm8996_ufsphy_serdes),
@@ -864,7 +867,7 @@ static const struct qmp_phy_cfg sa8775p_ufsphy_cfg = {
.lanes = 2,
.offsets = &qmp_ufs_offsets,
-
+ .max_hs_gear = UFS_HS_G4,
.tbls = {
.serdes = sm8350_ufsphy_serdes,
.serdes_num = ARRAY_SIZE(sm8350_ufsphy_serdes),
@@ -879,7 +882,7 @@ static const struct qmp_phy_cfg sa8775p_ufsphy_cfg = {
.serdes = sm8350_ufsphy_hs_b_serdes,
.serdes_num = ARRAY_SIZE(sm8350_ufsphy_hs_b_serdes),
},
- .tbls_hs_g4 = {
+ .tbls_hs_max = {
.tx = sm8350_ufsphy_g4_tx,
.tx_num = ARRAY_SIZE(sm8350_ufsphy_g4_tx),
.rx = sm8350_ufsphy_g4_rx,
@@ -898,7 +901,7 @@ static const struct qmp_phy_cfg sc8280xp_ufsphy_cfg = {
.lanes = 2,
.offsets = &qmp_ufs_offsets,
-
+ .max_hs_gear = UFS_HS_G4,
.tbls = {
.serdes = sm8350_ufsphy_serdes,
.serdes_num = ARRAY_SIZE(sm8350_ufsphy_serdes),
@@ -913,7 +916,7 @@ static const struct qmp_phy_cfg sc8280xp_ufsphy_cfg = {
.serdes = sm8350_ufsphy_hs_b_serdes,
.serdes_num = ARRAY_SIZE(sm8350_ufsphy_hs_b_serdes),
},
- .tbls_hs_g4 = {
+ .tbls_hs_max = {
.tx = sm8350_ufsphy_g4_tx,
.tx_num = ARRAY_SIZE(sm8350_ufsphy_g4_tx),
.rx = sm8350_ufsphy_g4_rx,
@@ -932,7 +935,7 @@ static const struct qmp_phy_cfg sdm845_ufsphy_cfg = {
.lanes = 2,
.offsets = &qmp_ufs_offsets,
-
+ .max_hs_gear = UFS_HS_G3,
.tbls = {
.serdes = sdm845_ufsphy_serdes,
.serdes_num = ARRAY_SIZE(sdm845_ufsphy_serdes),
@@ -960,7 +963,7 @@ static const struct qmp_phy_cfg sm6115_ufsphy_cfg = {
.lanes = 1,
.offsets = &qmp_ufs_offsets,
-
+ .max_hs_gear = UFS_HS_G3,
.tbls = {
.serdes = sm6115_ufsphy_serdes,
.serdes_num = ARRAY_SIZE(sm6115_ufsphy_serdes),
@@ -988,7 +991,7 @@ static const struct qmp_phy_cfg sm7150_ufsphy_cfg = {
.lanes = 1,
.offsets = &qmp_ufs_offsets,
-
+ .max_hs_gear = UFS_HS_G3,
.tbls = {
.serdes = sdm845_ufsphy_serdes,
.serdes_num = ARRAY_SIZE(sdm845_ufsphy_serdes),
@@ -1016,7 +1019,7 @@ static const struct qmp_phy_cfg sm8150_ufsphy_cfg = {
.lanes = 2,
.offsets = &qmp_ufs_offsets,
-
+ .max_hs_gear = UFS_HS_G4,
.tbls = {
.serdes = sm8150_ufsphy_serdes,
.serdes_num = ARRAY_SIZE(sm8150_ufsphy_serdes),
@@ -1031,7 +1034,7 @@ static const struct qmp_phy_cfg sm8150_ufsphy_cfg = {
.serdes = sm8150_ufsphy_hs_b_serdes,
.serdes_num = ARRAY_SIZE(sm8150_ufsphy_hs_b_serdes),
},
- .tbls_hs_g4 = {
+ .tbls_hs_max = {
.tx = sm8150_ufsphy_hs_g4_tx,
.tx_num = ARRAY_SIZE(sm8150_ufsphy_hs_g4_tx),
.rx = sm8150_ufsphy_hs_g4_rx,
@@ -1050,7 +1053,7 @@ static const struct qmp_phy_cfg sm8250_ufsphy_cfg = {
.lanes = 2,
.offsets = &qmp_ufs_offsets,
-
+ .max_hs_gear = UFS_HS_G4,
.tbls = {
.serdes = sm8150_ufsphy_serdes,
.serdes_num = ARRAY_SIZE(sm8150_ufsphy_serdes),
@@ -1065,7 +1068,7 @@ static const struct qmp_phy_cfg sm8250_ufsphy_cfg = {
.serdes = sm8150_ufsphy_hs_b_serdes,
.serdes_num = ARRAY_SIZE(sm8150_ufsphy_hs_b_serdes),
},
- .tbls_hs_g4 = {
+ .tbls_hs_max = {
.tx = sm8250_ufsphy_hs_g4_tx,
.tx_num = ARRAY_SIZE(sm8250_ufsphy_hs_g4_tx),
.rx = sm8250_ufsphy_hs_g4_rx,
@@ -1084,7 +1087,7 @@ static const struct qmp_phy_cfg sm8350_ufsphy_cfg = {
.lanes = 2,
.offsets = &qmp_ufs_offsets,
-
+ .max_hs_gear = UFS_HS_G4,
.tbls = {
.serdes = sm8350_ufsphy_serdes,
.serdes_num = ARRAY_SIZE(sm8350_ufsphy_serdes),
@@ -1099,7 +1102,7 @@ static const struct qmp_phy_cfg sm8350_ufsphy_cfg = {
.serdes = sm8350_ufsphy_hs_b_serdes,
.serdes_num = ARRAY_SIZE(sm8350_ufsphy_hs_b_serdes),
},
- .tbls_hs_g4 = {
+ .tbls_hs_max = {
.tx = sm8350_ufsphy_g4_tx,
.tx_num = ARRAY_SIZE(sm8350_ufsphy_g4_tx),
.rx = sm8350_ufsphy_g4_rx,
@@ -1118,7 +1121,7 @@ static const struct qmp_phy_cfg sm8450_ufsphy_cfg = {
.lanes = 2,
.offsets = &qmp_ufs_offsets,
-
+ .max_hs_gear = UFS_HS_G4,
.tbls = {
.serdes = sm8350_ufsphy_serdes,
.serdes_num = ARRAY_SIZE(sm8350_ufsphy_serdes),
@@ -1133,7 +1136,7 @@ static const struct qmp_phy_cfg sm8450_ufsphy_cfg = {
.serdes = sm8350_ufsphy_hs_b_serdes,
.serdes_num = ARRAY_SIZE(sm8350_ufsphy_hs_b_serdes),
},
- .tbls_hs_g4 = {
+ .tbls_hs_max = {
.tx = sm8350_ufsphy_g4_tx,
.tx_num = ARRAY_SIZE(sm8350_ufsphy_g4_tx),
.rx = sm8350_ufsphy_g4_rx,
@@ -1152,7 +1155,7 @@ static const struct qmp_phy_cfg sm8550_ufsphy_cfg = {
.lanes = 2,
.offsets = &qmp_ufs_offsets_v6,
-
+ .max_hs_gear = UFS_HS_G4,
.tbls = {
.serdes = sm8550_ufsphy_serdes,
.serdes_num = ARRAY_SIZE(sm8550_ufsphy_serdes),
@@ -1235,11 +1238,11 @@ static void qmp_ufs_init_registers(struct qmp_ufs *qmp, const struct qmp_phy_cfg
if (qmp->mode == PHY_MODE_UFS_HS_B)
qmp_ufs_serdes_init(qmp, &cfg->tbls_hs_b);
qmp_ufs_lanes_init(qmp, &cfg->tbls);
- if (qmp->submode == UFS_HS_G4)
- qmp_ufs_lanes_init(qmp, &cfg->tbls_hs_g4);
+ if (qmp->submode == cfg->max_hs_gear)
+ qmp_ufs_lanes_init(qmp, &cfg->tbls_hs_max);
qmp_ufs_pcs_init(qmp, &cfg->tbls);
- if (qmp->submode == UFS_HS_G4)
- qmp_ufs_pcs_init(qmp, &cfg->tbls_hs_g4);
+ if (qmp->submode == cfg->max_hs_gear)
+ qmp_ufs_pcs_init(qmp, &cfg->tbls_hs_max);
}
static int qmp_ufs_com_init(struct qmp_ufs *qmp)
--
2.7.4
next prev parent reply other threads:[~2023-11-22 7:11 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-11-22 7:10 [PATCH v3 00/11] Enable HS-G5 support on SM8550 Can Guo
2023-11-22 7:10 ` [PATCH v3 01/11] scsi: ufs: host: Rename structure ufs_dev_params to ufs_host_params Can Guo
2023-11-22 7:10 ` [PATCH v3 02/11] scsi: ufs: ufs-qcom: No need to set hs_rate after ufshcd_init_host_param() Can Guo
2023-11-22 7:10 ` [PATCH v3 03/11] scsi: ufs: ufs-qcom: Setup host power mode during init Can Guo
2023-11-22 7:10 ` [PATCH v3 04/11] scsi: ufs: ufs-qcom: Limit negotiated gear to selected PHY gear Can Guo
2023-11-22 7:10 ` [PATCH v3 05/11] scsi: ufs: ufs-qcom: Allow the first init start with the maximum supported gear Can Guo
2023-11-22 7:10 ` [PATCH v3 06/11] scsi: ufs: ufs-qcom: Limit HS-G5 Rate-A to hosts with HW version 5 Can Guo
2023-11-22 7:10 ` [PATCH v3 07/11] scsi: ufs: ufs-qcom: Set initial PHY gear to max HS gear for HW ver 5 and newer Can Guo
2023-11-22 7:10 ` [PATCH v3 08/11] phy: qualcomm: phy-qcom-qmp-ufs: Rectify SM8550 UFS HS-G4 PHY Settings Can Guo
2023-11-22 8:32 ` Dmitry Baryshkov
2023-11-22 9:02 ` Abel Vesa
2023-11-22 7:10 ` Can Guo [this message]
2023-11-22 7:10 ` [PATCH v3 10/11] phy: qualcomm: phy-qcom-qmp-ufs: Add High Speed Gear 5 support for SM8550 Can Guo
2023-11-22 9:07 ` Dmitry Baryshkov
2023-11-22 9:31 ` Can Guo
2023-11-22 9:52 ` Dmitry Baryshkov
2023-11-22 7:10 ` [PATCH v3 11/11] scsi: ufs: ufs-qcom: Add support for UFS device version detection Can Guo
2023-11-22 16:17 ` [PATCH v3 00/11] Enable HS-G5 support on SM8550 Andrew Halaney
2023-11-23 7:13 ` Can Guo
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