From: "tip-bot2 for Claudiu Beznea" <tip-bot2@linutronix.de>
To: linux-tip-commits@vger.kernel.org
Cc: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>,
Thomas Gleixner <tglx@linutronix.de>,
x86@kernel.org, linux-kernel@vger.kernel.org, maz@kernel.org
Subject: [tip: irq/core] arm64: dts: renesas: r9108g045: Add IA55 interrupt controller node
Date: Fri, 08 Dec 2023 21:14:38 -0000 [thread overview]
Message-ID: <170207007858.398.5775493085982200914.tip-bot2@tip-bot2> (raw)
In-Reply-To: <20231120111820.87398-10-claudiu.beznea.uj@bp.renesas.com>
The following commit has been merged into the irq/core branch of tip:
Commit-ID: 8794f5c3d2299670d16b2fb1e6657f5f33c1518c
Gitweb: https://git.kernel.org/tip/8794f5c3d2299670d16b2fb1e6657f5f33c1518c
Author: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
AuthorDate: Mon, 20 Nov 2023 13:18:20 +02:00
Committer: Thomas Gleixner <tglx@linutronix.de>
CommitterDate: Fri, 08 Dec 2023 22:06:35 +01:00
arm64: dts: renesas: r9108g045: Add IA55 interrupt controller node
Add IA55 interrupt controller node and set it as interrupt parent for pin
controller.
Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Link: https://lore.kernel.org/r/20231120111820.87398-10-claudiu.beznea.uj@bp.renesas.com
---
arch/arm64/boot/dts/renesas/r9a08g045.dtsi | 68 +++++++++++++++++++++-
1 file changed, 68 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi
index 6c7b29b..010bca6 100644
--- a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi
@@ -96,6 +96,7 @@
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
+ interrupt-parent = <&irqc>;
gpio-ranges = <&pinctrl 0 0 152>;
clocks = <&cpg CPG_MOD R9A08G045_GPIO_HCLK>;
power-domains = <&cpg>;
@@ -104,6 +105,73 @@
<&cpg R9A08G045_GPIO_SPARE_RESETN>;
};
+ irqc: interrupt-controller@11050000 {
+ compatible = "renesas,r9a08g045-irqc", "renesas,rzg2l-irqc";
+ #interrupt-cells = <2>;
+ #address-cells = <0>;
+ interrupt-controller;
+ reg = <0 0x11050000 0 0x10000>;
+ interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 433 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 436 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 437 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 440 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 441 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 443 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 450 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 451 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 453 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 454 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 455 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 457 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 459 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 460 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "nmi",
+ "irq0", "irq1", "irq2", "irq3",
+ "irq4", "irq5", "irq6", "irq7",
+ "tint0", "tint1", "tint2", "tint3",
+ "tint4", "tint5", "tint6", "tint7",
+ "tint8", "tint9", "tint10", "tint11",
+ "tint12", "tint13", "tint14", "tint15",
+ "tint16", "tint17", "tint18", "tint19",
+ "tint20", "tint21", "tint22", "tint23",
+ "tint24", "tint25", "tint26", "tint27",
+ "tint28", "tint29", "tint30", "tint31",
+ "bus-err";
+ clocks = <&cpg CPG_MOD R9A08G045_IA55_CLK>,
+ <&cpg CPG_MOD R9A08G045_IA55_PCLK>;
+ clock-names = "clk", "pclk";
+ power-domains = <&cpg>;
+ resets = <&cpg R9A08G045_IA55_RESETN>;
+ };
+
sdhi0: mmc@11c00000 {
compatible = "renesas,sdhi-r9a08g045", "renesas,rcar-gen3-sdhi";
reg = <0x0 0x11c00000 0 0x10000>;
next prev parent reply other threads:[~2023-12-08 21:14 UTC|newest]
Thread overview: 39+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-11-20 11:18 [PATCH v3 0/9] irqchip/renesas-rzg2l: add support for RZ/G3S SoC Claudiu
2023-11-20 11:18 ` [PATCH v3 1/9] clk: renesas: r9a08g045: Add IA55 pclk and its reset Claudiu
2023-11-21 9:59 ` Geert Uytterhoeven
2023-11-21 11:03 ` claudiu beznea
2023-12-13 14:11 ` Geert Uytterhoeven
2023-12-08 21:14 ` [tip: irq/core] " tip-bot2 for Claudiu Beznea
2023-12-09 16:22 ` Geert Uytterhoeven
2023-11-20 11:18 ` [PATCH v3 2/9] irqchip/renesas-rzg2l: Use tabs instead of spaces Claudiu
2023-11-21 10:07 ` Geert Uytterhoeven
2023-12-08 21:14 ` [tip: irq/core] " tip-bot2 for Claudiu Beznea
2023-12-12 14:44 ` tip-bot2 for Claudiu Beznea
2023-11-20 11:18 ` [PATCH v3 3/9] irqchip/renesas-rzg2l: Align struct member names to tabs Claudiu
2023-11-21 10:09 ` Geert Uytterhoeven
2023-12-08 21:14 ` [tip: irq/core] " tip-bot2 for Claudiu Beznea
2023-12-12 14:44 ` tip-bot2 for Claudiu Beznea
2023-11-20 11:18 ` [PATCH v3 4/9] irqchip/renesas-rzg2l: Document structure members Claudiu
2023-11-21 10:10 ` Geert Uytterhoeven
2023-12-08 21:14 ` [tip: irq/core] " tip-bot2 for Claudiu Beznea
2023-12-12 14:44 ` tip-bot2 for Claudiu Beznea
2023-11-20 11:18 ` [PATCH v3 5/9] irqchip/renesas-rzg2l: Implement restriction when writing ISCR register Claudiu
2023-11-21 10:17 ` Geert Uytterhoeven
2023-12-08 21:14 ` [tip: irq/core] " tip-bot2 for Claudiu Beznea
2023-12-12 14:44 ` tip-bot2 for Claudiu Beznea
2023-11-20 11:18 ` [PATCH v3 6/9] irqchip/renesas-rzg2l: Add macro to retrieve TITSR register offset based on register's index Claudiu
2023-11-21 10:30 ` Geert Uytterhoeven
2023-12-08 21:14 ` [tip: irq/core] " tip-bot2 for Claudiu Beznea
2023-12-12 14:44 ` tip-bot2 for Claudiu Beznea
2023-11-20 11:18 ` [PATCH v3 7/9] irqchip/renesas-rzg2l: Add support for suspend to RAM Claudiu
2023-12-08 21:14 ` [tip: irq/core] " tip-bot2 for Claudiu Beznea
2023-12-12 14:44 ` tip-bot2 for Claudiu Beznea
2023-11-20 11:18 ` [PATCH v3 8/9] dt-bindings: interrupt-controller: renesas,rzg2l-irqc: Document RZ/G3S Claudiu
2023-11-21 10:44 ` Geert Uytterhoeven
2023-12-08 21:14 ` [tip: irq/core] " tip-bot2 for Claudiu Beznea
2023-12-12 14:44 ` tip-bot2 for Claudiu Beznea
2023-11-20 11:18 ` [PATCH v3 9/9] arm64: dts: renesas: r9108g045: Add IA55 interrupt controller node Claudiu
2023-12-08 21:14 ` tip-bot2 for Claudiu Beznea [this message]
2023-12-09 16:24 ` [tip: irq/core] " Geert Uytterhoeven
2023-12-12 14:41 ` Thomas Gleixner
2023-12-13 14:18 ` [PATCH v3 9/9] " Geert Uytterhoeven
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