From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752561AbbHTGpx (ORCPT ); Thu, 20 Aug 2015 02:45:53 -0400 Received: from mailout1.samsung.com ([203.254.224.24]:60067 "EHLO mailout1.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752433AbbHTGpu (ORCPT ); Thu, 20 Aug 2015 02:45:50 -0400 X-AuditID: cbfee68e-f79c56d000006efb-af-55d5779c7967 Date: Thu, 20 Aug 2015 06:40:46 +0000 (GMT) From: Sarbojit Ganguly Subject: Re: Re: [PATCH] arm: Adding support for atomic half word exchange To: Catalin Marinas , Sarbojit Ganguly , will.deacon@arm.com, linux-arm-kernel@lists.infradead.org Cc: SHARAN ALLUR , VIKRAM MUPPARTHI , "peterz@infradead.org" , "Waiman.Long@hp.com" , "linux-kernel@vger.kernel.org" , "torvalds@linux-foundation.org" Reply-to: ganguly.s@samsung.com MIME-version: 1.0 X-MTR: 20150820063139591@ganguly.s Msgkey: 20150820063139591@ganguly.s X-EPLocale: en_US.windows-1252 X-Priority: 3 X-EPWebmail-Msg-Type: personal X-EPWebmail-Reply-Demand: 0 X-EPApproval-Locale: X-EPHeader: ML X-MLAttribute: X-RootMTR: 20150820063139591@ganguly.s X-ParentMTR: X-ArchiveUser: X-CPGSPASS: Y X-ConfirmMail: N,general Content-type: text/plain; charset=windows-1252 MIME-version: 1.0 Message-id: <1707387422.329291440052843653.JavaMail.weblogic@ep2mlwas04c> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFvrGIsWRmVeSWpSXmKPExsWyRsSkTndO+dVQg03vpC0u75rD5sDo8XmT XABjFJdNSmpOZllqkb5dAldG19afrAWHZCoeLt3F1MD4QLqLkYNDSEBFom9SRBcjJ4eEgInE xFe/WCFsMYkL99azdTFyAZUsZZQ4eHYhE0xR99FfzBCJOYwSN3bcZwNJsAioSuxsfMsOYrMJ 6Euc3v8SrEFYwEviwetHYFNFBJYxSvx/yQPSzCywh0mi89ZpFpCEkIC8RPuL7WANvAKCEidn PmGB2KYk0XVgAhtEXFli1tRZzBBxOYklUy9DXcQrMaP9KQtMfNrXNVA10hLnZ21ghHln8ffH UHF+iWO3d0D1CkhMPXMQqkZdYunSi1Bz+CTWLHzLAlO/69RyZphdDRt/s0PYEhJbW56APcYs oCgxpfshO4RtIHFk0RxWdL/wCnhKHG78wg7yvITARA6J+y9eMU5gVJqFpG4WklmzkMxCVrOA kWUVo2hqQXJBcVJ6kZFecWJucWleul5yfu4mRmByOP3vWd8OxpsHrA8xCnAwKvHwrrS+GirE mlhWXJl7iNEUGFETmaVEk/OBKSivJN7Q2MzIwtTE1NjI3NJMSZw3QepnsJBAemJJanZqakFq UXxRaU5q8SFGJg5OqQbGkPYeb6df04x31/34M/1Bf9+/sgNMf3iTWtd/49FlcexLF+g69FAs iGfah5qbM6Ke7rYr9dnRrlkU/HPJ3sk5KRyvZqTMTeYqXTZx9bZVO9qMmrQ2bmnQPs335lIm p7TRsds/pk29Nn37RONDD032zPT8+04r09BqArPBSk3N4NWz+b80a0y4rMRSnJFoqMVcVJwI AOvVzdAJAwAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFjrOKsWRmVeSWpSXmKPExsVy+t/tXt28squhBkta+S0u75rD5sDo8XmT XABjVJpNRmpiSmqRQmpecn5KZl66rZJ3cLxzvKmZgaGuoaWFuZJCXmJuqq2Si0+ArltmDtBQ JYWyxJxSoFBAYnGxkr6dTVF+aUmqQkZ+cYmtUrShuZGekYGeqZGeoWmslaGBgZEpUE1CWkbX 1p+sBYdkKh4u3cXUwPhAuouRg0NIQEWib1JEFyMnh4SAiUT30V/MELaYxIV769m6GLmASuYw StzYcZ8NJMEioCqxs/EtO4jNJqAvcXr/SyYQW1jAS+LB60esILaIwDJGif8veUCamQX2MEl0 3jrNApIQEpCXaH+xHayBV0BQ4uTMJywQ25Qkug5MYIOIK0vMmjoL6go5iSVTLzNB2LwSM9qf ssDEp31dA1UjLXF+1gZGmKsXf38MFeeXOHZ7B1SvgMTUMwehatQlli69CDWHT2LNwrcsMPW7 Ti1nhtnVsPE3O4QtIbG15QnYY8wCihJTuh+yQ9gGEkcWzWFF9wuvgKfE4cYv7BMYZWchSc1C 0j4LSTuymgWMLKsYRVMLkguKk9IrjPWKE3OLS/PS9ZLzczcxghPRs8U7GP+ftz7EKMDBqMTD qyF2NVSINbGsuDL3EKMEB7OSCK+fDlCINyWxsiq1KD++qDQntfgQoykw2iYyS4km5wOTZF5J vKGxibmpsamFgaG5uZmSOO//c7khQgLpiSWp2ampBalFMH1MHJxSDYwcvkIh31e5x/1xajTw eiS39uiX0iU5Us/EVu+8/TP9tLdt3MeNV9bofNLnUjAQtJzxnVU8xMutq2269ZkNLvGFs/we zY9aX6+Yk325ebXc5wot7ztXDe9Lt955uVo6WuqrW1RSS5gtn65+eFXH4r/1VeKu28ramOZ/ Obpli/ei0xyiui97NZRYijMSDbWYi4oTAT1/jidaAwAA DLP-Filter: Pass X-CFilter-Loop: Reflected Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: 8bit X-MIME-Autoconverted: from base64 to 8bit by mail.home.local id t7K6jvgs025810 My apologies, the e-mail editor was not configured properly. CC'ed to relevant maintainers and reposting once again with proper formatting. Since 16 bit half word exchange was not there and MCS based qspinlock by Waiman's xchg_tail() requires an atomic exchange on a half word, here is a small modification to __xchg() code to support the exchange. ARMv6 and lower does not have support for LDREXH, so we need to make sure things do not break when we're compiling on ARMv6. Signed-off-by: Sarbojit Ganguly --- arch/arm/include/asm/cmpxchg.h | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/arch/arm/include/asm/cmpxchg.h b/arch/arm/include/asm/cmpxchg.h index 1692a05..547101d 100644 --- a/arch/arm/include/asm/cmpxchg.h +++ b/arch/arm/include/asm/cmpxchg.h @@ -50,6 +50,24 @@ static inline unsigned long __xchg(unsigned long x, volatile void *ptr, int size : "r" (x), "r" (ptr) : "memory", "cc"); break; +#if !defined (CONFIG_CPU_V6) + /* + * Halfword exclusive exchange + * This is new implementation as qspinlock + * wants 16 bit atomic CAS. + * This is not supported on ARMv6. + */ + case 2: + asm volatile("@ __xchg2\n" + "1: ldrexh %0, [%3]\n" + " strexh %1, %2, [%3]\n" + " teq %1, #0\n" + " bne 1b" + : "=&r" (ret), "=&r" (tmp) + : "r" (x), "r" (ptr) + : "memory", "cc"); + break; +#endif case 4: asm volatile("@ __xchg4\n" "1: ldrex %0, [%3]\n" Regards, Sarbojit ------- Original Message ------- Sender : Catalin Marinas Date : Aug 19, 2015 21:43 (GMT+05:30) Title : Re: [PATCH] arm: Adding support for atomic half word exchange On Tue, Aug 18, 2015 at 09:17:53AM +0100, Sarbojit Ganguly wrote: > > > Since 16 bit half word exchange was not there and MCS based qspinlock by Waiman's xchg_tail() requires an atomic exchange on a half word, here is a small modification to __xchg() code to support the exchange. > ARMv6 and lower does not have support for LDREXH, so we need to make sure things do not break when we're compiling on ARMv6. First of all, please wrap the text appropriately. Secondly, you need to cc the relevant maintainer and mailing list (try running ./scripts/get_maintainer.pl on this patch to get some hints). -- Catalin{.n++%ݶw{.n+{G{ayʇڙ,jfhz_(階ݢj"mG?&~iOzv^m ?I