From: Paul Mackerras <paulus@samba.org>
To: Marcelo Tosatti <marcelo.tosatti@cyclades.com>
Cc: linux-kernel@vger.kernel.org, Benjamin LaHaise <bcrl@kvack.org>
Subject: Re: increased translation cache footprint in v2.6
Date: Mon, 27 Jun 2005 09:42:52 +1000 [thread overview]
Message-ID: <17087.15740.442831.617781@cargo.ozlabs.ibm.com> (raw)
In-Reply-To: <20050626172334.GA5786@logos.cnet>
Marcelo Tosatti writes:
> We've noticed a slowdown while moving from v2.4 to v2.6 on a small PPC platform
> (855T CPU running at 48Mhz, containing pair of separate I/D TLB caches with
> 32 entries each), with a relatively recent kernel (v2.6.11).
>
> Test in question is a "dd" copying 16MB from /dev/zero to RAMDISK.
>
> Pinning an 8Mbyte TLB entry at KERNELBASE brought performance back to v2.4 levels.
Why are we not pinning a large TLB entry at KERNELBASE in 2.6? Was
that taken out to reduce the size of the tlb miss handler or
something?
Paul.
next prev parent reply other threads:[~2005-06-26 23:50 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2005-06-26 17:23 Marcelo Tosatti
2005-06-26 23:42 ` Paul Mackerras [this message]
2005-06-26 18:31 ` Marcelo Tosatti
2005-06-26 23:49 ` Andrew Morton
2005-06-26 18:52 ` Marcelo Tosatti
2005-06-27 0:33 ` David S. Miller
2005-06-26 19:09 ` Marcelo Tosatti
2005-06-27 0:53 ` David S. Miller
2005-06-27 15:57 ` Dan Malek
2005-06-27 19:50 ` David S. Miller
2005-06-27 20:35 ` Dan Malek
2005-06-28 6:18 ` Benjamin Herrenschmidt
2005-06-28 13:42 ` Dan Malek
2005-06-27 15:46 ` Dan Malek
2005-06-28 6:21 ` Benjamin Herrenschmidt
2005-06-28 13:49 ` Dan Malek
2005-06-27 1:55 ` Benjamin Herrenschmidt
2005-06-27 19:04 Al Boldi
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