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From: Vinod Koul <vkoul@kernel.org>
To: Kishon Vijay Abraham I <kishon@kernel.org>, 
 Rob Herring <robh@kernel.org>, Krzysztof Kozlowski <krzk+dt@kernel.org>, 
 Conor Dooley <conor+dt@kernel.org>, 
 Peter Griffin <peter.griffin@linaro.org>, 
 Marek Szyprowski <m.szyprowski@samsung.com>, 
 Sylwester Nawrocki <s.nawrocki@samsung.com>, 
 Alim Akhtar <alim.akhtar@samsung.com>, 
 Sam Protsenko <semen.protsenko@linaro.org>, 
 =?utf-8?q?Andr=C3=A9_Draszik?= <andre.draszik@linaro.org>
Cc: Krzysztof Kozlowski <krzk@kernel.org>, 
 Tudor Ambarus <tudor.ambarus@linaro.org>, 
 Will McVicker <willmcvicker@google.com>, Roy Luo <royluo@google.com>, 
 kernel-team@android.com, linux-phy@lists.infradead.org, 
 devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, 
 linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org
In-Reply-To: <20240617-usb-phy-gs101-v3-0-b66de9ae7424@linaro.org>
References: <20240617-usb-phy-gs101-v3-0-b66de9ae7424@linaro.org>
Subject: Re: [PATCH v3 0/6] USB31DRD phy support for Google Tensor gs101
 (HS & SS)
Message-Id: <171992736365.699169.8645962740649153976.b4-ty@kernel.org>
Date: Tue, 02 Jul 2024 19:06:03 +0530
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On Mon, 17 Jun 2024 17:44:41 +0100, André Draszik wrote:
> This patch series adds support for the Exynos USB 3.1 DRD combo phy, as
> found in Exynos 9 SoCs like Google GS101. It supports USB SS, HS and
> DisplayPort, but DisplayPort is out of scope for this series.
> 
> In terms of UTMI+, this is very similar to the existing Exynos850
> support in this driver. The difference is that it supports both UTMI+
> (HS) and PIPE3 (SS). Firstly, there are some preparatory patches to convert
> this driver to using the clk_bulk and regulator_bulk APIs to simplify
> addition, while the bulk of the changes is around the SS part.
> 
> [...]

Applied, thanks!

[1/6] dt-bindings: phy: samsung,usb3-drd-phy: add gs101 compatible
      commit: e340c041b7a4c0321bfe2cb54817837c9040c739
[2/6] phy: exynos5-usbdrd: support isolating HS and SS ports independently
      commit: bbb28a1d733a94330f5778b4cd0dbccf6c34597d
[3/6] phy: exynos5-usbdrd: convert core clocks to clk_bulk
      commit: 54290bd9811ecdd82c19b96093e2c78325f59574
[4/6] phy: exynos5-usbdrd: convert (phy) register access clock to clk_bulk
      commit: 26ba3261215b44d466bd2093daf3796031c09c0a
[5/6] phy: exynos5-usbdrd: convert Vbus supplies to regulator_bulk
      commit: 497ddafe915e8d9fb4d11542d16a1ff95a3e8034
[6/6] phy: exynos5-usbdrd: support Exynos USBDRD 3.1 combo phy (HS & SS)
      commit: 32267c29bc7d5c9654b71e4f354064217a5fb053

Best regards,
-- 
Vinod Koul <vkoul@kernel.org>