From: Will Deacon <will@kernel.org>
To: Marc Zyngier <maz@kernel.org>,
Russell King <linux@armlinux.org.uk>,
Catalin Marinas <catalin.marinas@arm.com>,
Mark Rutland <mark.rutland@arm.com>,
"Rob Herring (Arm)" <robh@kernel.org>
Cc: kernel-team@android.com, Will Deacon <will@kernel.org>,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH] perf/arm_pmuv3: Add PMUv3.9 per counter EL0 access control
Date: Mon, 28 Oct 2024 18:52:21 +0000 [thread overview]
Message-ID: <173013643645.2908148.3061264044552373982.b4-ty@kernel.org> (raw)
In-Reply-To: <20241002184326.1105499-1-robh@kernel.org>
On Wed, 02 Oct 2024 13:43:24 -0500, Rob Herring (Arm) wrote:
> Armv8.9/9.4 PMUv3.9 adds per counter EL0 access controls. Per counter
> access is enabled with the UEN bit in PMUSERENR_EL1 register. Individual
> counters are enabled/disabled in the PMUACR_EL1 register. When UEN is
> set, the CR/ER bits control EL0 write access and must be set to disable
> write access.
>
> With the access controls, the clearing of unused counters can be
> skipped.
>
> [...]
Applied to will (for-next/perf), thanks!
[1/1] perf/arm_pmuv3: Add PMUv3.9 per counter EL0 access control
https://git.kernel.org/will/c/0bbff9ed8165
Cheers,
--
Will
https://fixes.arm64.dev
https://next.arm64.dev
https://will.arm64.dev
prev parent reply other threads:[~2024-10-28 18:52 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-10-02 18:43 Rob Herring (Arm)
2024-10-24 10:39 ` Will Deacon
2024-10-24 16:41 ` Rob Herring
2024-10-28 17:26 ` Will Deacon
2024-10-28 18:52 ` Will Deacon [this message]
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