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From: "tip-bot2 for Paul Burton" <tip-bot2@linutronix.de>
To: linux-tip-commits@vger.kernel.org
Cc: Paul Burton <paulburton@kernel.org>,
	"Chao-ying Fu" <cfu@wavecomp.com>,
	Dragan Mladjenovic <dragan.mladjenovic@syrmia.com>,
	Aleksandar Rikalo <arikalo@gmail.com>,
	Thomas Gleixner <tglx@linutronix.de>,
	Serge Semin <fancer.lancer@gmail.com>,
	Gregory CLEMENT <gregory.clement@bootlin.com>,
	x86@kernel.org, linux-kernel@vger.kernel.org, maz@kernel.org
Subject: [tip: irq/core] irqchip/mips-gic: Replace open coded online CPU iterations
Date: Wed, 30 Oct 2024 14:49:53 -0000	[thread overview]
Message-ID: <173029979395.3137.3954011686630855852.tip-bot2@tip-bot2> (raw)
In-Reply-To: <20241028175935.51250-2-arikalo@gmail.com>

The following commit has been merged into the irq/core branch of tip:

Commit-ID:     496461050b74d44a2adb39511403a36c9a555bc7
Gitweb:        https://git.kernel.org/tip/496461050b74d44a2adb39511403a36c9a555bc7
Author:        Paul Burton <paulburton@kernel.org>
AuthorDate:    Mon, 28 Oct 2024 18:59:23 +01:00
Committer:     Thomas Gleixner <tglx@linutronix.de>
CommitterDate: Wed, 30 Oct 2024 15:41:18 +01:00

irqchip/mips-gic: Replace open coded online CPU iterations

Several places in the MIPS GIC driver iterate over the online CPUs to
operate on the CPU's GIC local register block, accessed via the GIC's
other/redirect register block.

Abstract the process of iterating over online CPUs & configuring the
other/redirect region to access their registers through a new
for_each_online_cpu_gic() macro and convert all usage sites over.

Signed-off-by: Paul Burton <paulburton@kernel.org>
Signed-off-by: Chao-ying Fu <cfu@wavecomp.com>
Signed-off-by: Dragan Mladjenovic <dragan.mladjenovic@syrmia.com>
Signed-off-by: Aleksandar Rikalo <arikalo@gmail.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Tested-by: Serge Semin <fancer.lancer@gmail.com>
Tested-by: Gregory CLEMENT <gregory.clement@bootlin.com>
Link: https://lore.kernel.org/all/20241028175935.51250-2-arikalo@gmail.com

---
 drivers/irqchip/irq-mips-gic.c | 59 ++++++++++++++++++++++-----------
 1 file changed, 41 insertions(+), 18 deletions(-)

diff --git a/drivers/irqchip/irq-mips-gic.c b/drivers/irqchip/irq-mips-gic.c
index 76253e8..6c7a7d2 100644
--- a/drivers/irqchip/irq-mips-gic.c
+++ b/drivers/irqchip/irq-mips-gic.c
@@ -66,6 +66,44 @@ static struct gic_all_vpes_chip_data {
 	bool	mask;
 } gic_all_vpes_chip_data[GIC_NUM_LOCAL_INTRS];
 
+static int __gic_with_next_online_cpu(int prev)
+{
+	unsigned int cpu;
+
+	/* Discover the next online CPU */
+	cpu = cpumask_next(prev, cpu_online_mask);
+
+	/* If there isn't one, we're done */
+	if (cpu >= nr_cpu_ids)
+		return cpu;
+
+	/*
+	 * Move the access lock to the next CPU's GIC local register block.
+	 *
+	 * Set GIC_VL_OTHER. Since the caller holds gic_lock nothing can
+	 * clobber the written value.
+	 */
+	write_gic_vl_other(mips_cm_vp_id(cpu));
+
+	return cpu;
+}
+
+/**
+ * for_each_online_cpu_gic() - Iterate over online CPUs, access local registers
+ * @cpu: An integer variable to hold the current CPU number
+ * @gic_lock: A pointer to raw spin lock used as a guard
+ *
+ * Iterate over online CPUs & configure the other/redirect register region to
+ * access each CPUs GIC local register block, which can be accessed from the
+ * loop body using read_gic_vo_*() or write_gic_vo_*() accessor functions or
+ * their derivatives.
+ */
+#define for_each_online_cpu_gic(cpu, gic_lock)		\
+	guard(raw_spinlock_irqsave)(gic_lock);		\
+	for ((cpu) = __gic_with_next_online_cpu(-1);	\
+	     (cpu) < nr_cpu_ids;			\
+	     (cpu) = __gic_with_next_online_cpu(cpu))
+
 static void gic_clear_pcpu_masks(unsigned int intr)
 {
 	unsigned int i;
@@ -350,37 +388,27 @@ static struct irq_chip gic_local_irq_controller = {
 static void gic_mask_local_irq_all_vpes(struct irq_data *d)
 {
 	struct gic_all_vpes_chip_data *cd;
-	unsigned long flags;
 	int intr, cpu;
 
 	intr = GIC_HWIRQ_TO_LOCAL(d->hwirq);
 	cd = irq_data_get_irq_chip_data(d);
 	cd->mask = false;
 
-	raw_spin_lock_irqsave(&gic_lock, flags);
-	for_each_online_cpu(cpu) {
-		write_gic_vl_other(mips_cm_vp_id(cpu));
+	for_each_online_cpu_gic(cpu, &gic_lock)
 		write_gic_vo_rmask(BIT(intr));
-	}
-	raw_spin_unlock_irqrestore(&gic_lock, flags);
 }
 
 static void gic_unmask_local_irq_all_vpes(struct irq_data *d)
 {
 	struct gic_all_vpes_chip_data *cd;
-	unsigned long flags;
 	int intr, cpu;
 
 	intr = GIC_HWIRQ_TO_LOCAL(d->hwirq);
 	cd = irq_data_get_irq_chip_data(d);
 	cd->mask = true;
 
-	raw_spin_lock_irqsave(&gic_lock, flags);
-	for_each_online_cpu(cpu) {
-		write_gic_vl_other(mips_cm_vp_id(cpu));
+	for_each_online_cpu_gic(cpu, &gic_lock)
 		write_gic_vo_smask(BIT(intr));
-	}
-	raw_spin_unlock_irqrestore(&gic_lock, flags);
 }
 
 static void gic_all_vpes_irq_cpu_online(void)
@@ -469,7 +497,6 @@ static int gic_irq_domain_map(struct irq_domain *d, unsigned int virq,
 			      irq_hw_number_t hwirq)
 {
 	struct gic_all_vpes_chip_data *cd;
-	unsigned long flags;
 	unsigned int intr;
 	int err, cpu;
 	u32 map;
@@ -533,12 +560,8 @@ static int gic_irq_domain_map(struct irq_domain *d, unsigned int virq,
 	if (!gic_local_irq_is_routable(intr))
 		return -EPERM;
 
-	raw_spin_lock_irqsave(&gic_lock, flags);
-	for_each_online_cpu(cpu) {
-		write_gic_vl_other(mips_cm_vp_id(cpu));
+	for_each_online_cpu_gic(cpu, &gic_lock)
 		write_gic_vo_map(mips_gic_vx_map_reg(intr), map);
-	}
-	raw_spin_unlock_irqrestore(&gic_lock, flags);
 
 	return 0;
 }

  reply	other threads:[~2024-10-30 14:49 UTC|newest]

Thread overview: 34+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-10-28 17:59 [PATCH v8 00/13] MIPS: Support I6500 multi-cluster configuration Aleksandar Rikalo
2024-10-28 17:59 ` [PATCH v8 01/13] irqchip/mips-gic: Introduce for_each_online_cpu_gic() Aleksandar Rikalo
2024-10-30 14:49   ` tip-bot2 for Paul Burton [this message]
2024-10-28 17:59 ` [PATCH v8 02/13] irqchip/mips-gic: Support multi-cluster in for_each_online_cpu_gic() Aleksandar Rikalo
2024-10-30 14:49   ` [tip: irq/core] " tip-bot2 for Paul Burton
2024-10-28 17:59 ` [PATCH v8 03/13] irqchip/mips-gic: Setup defaults in each cluster Aleksandar Rikalo
2024-10-30 14:49   ` [tip: irq/core] " tip-bot2 for Chao-ying Fu
2024-10-28 17:59 ` [PATCH v8 04/13] irqchip/mips-gic: Multi-cluster support Aleksandar Rikalo
2024-10-28 19:45   ` Thomas Gleixner
2024-10-30 14:49   ` [tip: irq/core] " tip-bot2 for Paul Burton
2024-10-28 17:59 ` [PATCH v8 05/13] clocksource: mips-gic-timer: Always use cluster 0 counter as clocksource Aleksandar Rikalo
2024-10-28 17:59 ` [PATCH v8 06/13] clocksource: mips-gic-timer: Enable counter when CPUs start Aleksandar Rikalo
2024-10-28 17:59 ` [PATCH v8 07/13] MIPS: pm-cps: Use per-CPU variables as per-CPU, not per-core Aleksandar Rikalo
2024-10-28 17:59 ` [PATCH v8 08/13] MIPS: CPS: Introduce struct cluster_boot_config Aleksandar Rikalo
2024-10-28 17:59 ` [PATCH v8 09/13] MIPS: CPS: Boot CPUs in secondary clusters Aleksandar Rikalo
2024-10-28 17:59 ` [PATCH v8 10/13] dt-bindings: mips: cpu: Add property for broken HCI information Aleksandar Rikalo
2024-10-29  7:03   ` Krzysztof Kozlowski
2024-10-29 12:21     ` Aleksandar Rikalo
2024-10-29 16:08       ` Gregory CLEMENT
2024-10-29 16:11       ` Jiaxun Yang
2024-10-30 11:35         ` Jiaxun Yang
2024-10-31  8:13           ` Gregory CLEMENT
2024-10-31 14:42             ` Thomas Bogendoerfer
2024-10-31 15:27               ` Jiaxun Yang
2024-10-28 17:59 ` [PATCH v8 11/13] MIPS: CPS: Support broken HCI for multicluster Aleksandar Rikalo
2024-10-28 17:59 ` [PATCH v8 12/13] MIPS: mobileye: dts: eyeq6h: Enable cluster support Aleksandar Rikalo
2024-10-28 17:59 ` [PATCH v8 13/13] irqchip: mips-gic: Handle case with cluster without CPU cores Aleksandar Rikalo
2024-10-30 14:49   ` [tip: irq/core] irqchip/mips-gic: Prevent indirect access to clusters " tip-bot2 for Gregory CLEMENT
2024-10-30 11:39 ` [PATCH v8 00/13] MIPS: Support I6500 multi-cluster configuration Jiaxun Yang
2024-11-01  1:47   ` Maciej W. Rozycki
2025-01-22 15:06 ` Gregory CLEMENT
2025-01-23 10:19   ` Aleksandar Rikalo
2025-01-23 15:35     ` Gregory CLEMENT
2025-02-19 10:46       ` Aleksandar Rikalo

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