From: "Rob Herring (Arm)" <robh@kernel.org>
To: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
Cc: "Thomas Zimmermann" <tzimmermann@suse.de>,
"Maxime Ripard" <mripard@kernel.org>,
"Maarten Lankhorst" <maarten.lankhorst@linux.intel.com>,
"David Airlie" <airlied@gmail.com>,
devicetree@vger.kernel.org, kernel@collabora.com,
"Sandy Huang" <hjc@rock-chips.com>,
linux-arm-kernel@lists.infradead.org,
dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org,
linux-rockchip@lists.infradead.org,
"Conor Dooley" <conor+dt@kernel.org>,
"Heiko Stübner" <heiko@sntech.de>,
"Andy Yan" <andy.yan@rock-chips.com>,
"Krzysztof Kozlowski" <krzk+dt@kernel.org>,
"Simona Vetter" <simona@ffwll.ch>
Subject: Re: [PATCH 1/5] dt-bindings: display: vop2: Add optional PLL clock properties
Date: Tue, 19 Nov 2024 11:14:58 -0600 [thread overview]
Message-ID: <173203649757.1839089.16877007589155949446.robh@kernel.org> (raw)
In-Reply-To: <20241116-vop2-hdmi0-disp-modes-v1-1-2bca51db4898@collabora.com>
On Sat, 16 Nov 2024 20:22:32 +0200, Cristian Ciocaltea wrote:
> On RK3588, HDMI PHY PLL can be used as an alternative and more accurate
> pixel clock source for VOP2 video ports 0, 1 and 2.
>
> Document the optional PLL clock properties corresponding to the two HDMI
> PHYs available on the SoC.
>
> Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
> ---
> Documentation/devicetree/bindings/display/rockchip/rockchip-vop2.yaml | 4 ++++
> 1 file changed, 4 insertions(+)
>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
next prev parent reply other threads:[~2024-11-19 17:15 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-11-16 18:22 [PATCH 0/5] Improve Rockchip VOP2 display modes handling on RK3588 HDMI0 Cristian Ciocaltea
2024-11-16 18:22 ` [PATCH 1/5] dt-bindings: display: vop2: Add optional PLL clock properties Cristian Ciocaltea
2024-11-19 17:14 ` Rob Herring (Arm) [this message]
2024-11-16 18:22 ` [PATCH 2/5] drm/rockchip: vop2: Drop unnecessary if_pixclk_rate computation Cristian Ciocaltea
2024-11-16 18:22 ` [PATCH 3/5] drm/rockchip: vop2: Improve display modes handling on RK3588 HDMI0 Cristian Ciocaltea
2024-11-16 19:12 ` Jonas Karlman
2024-11-16 23:22 ` Cristian Ciocaltea
2024-11-16 18:22 ` [PATCH 4/5] arm64: dts: rockchip: Enable HDMI0 PHY clk provider on RK3588 Cristian Ciocaltea
2024-11-16 18:22 ` [PATCH 5/5] arm64: dts: rockchip: Add HDMI0 PHY PLL clock source to VOP2 " Cristian Ciocaltea
2024-11-20 22:16 ` [PATCH 0/5] Improve Rockchip VOP2 display modes handling on RK3588 HDMI0 FUKAUMI Naoki
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