From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5F3361DA113; Thu, 26 Dec 2024 22:39:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1735252753; cv=none; b=ayysMAxqOpLLQ+0N3eEvST20LclzahzbTKo8eYDVt88L3CkdP+yKl/eNxhnrrnoFuYEE76tiAyxU4pr31sYKaa72qL9tXLFA0vlSWjvDC6uMui4btaK8N5yawewdhrN+p8jJ5PR4pRBQwT4my/pp0RxRrKZN6TxGAOanSY/Xnvo= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1735252753; c=relaxed/simple; bh=zzHpg02nt2xCzx11z3qrPTPt9BM7ACn4sX/GXztIxTA=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=oTi/A7gBVDCLZzbrmEqlpWcV6Wm9fw9T310CBKSGdgwOtccLfaSls+rd7nzYm99YZdOLfmuP/DtZY3YK4MyGyn7hnLu1tqT/MajbWqqTL6woDdMUul+6mwfEzskvb0EijIOjkkHpGzLF20zbJHlKy3b8c9O5C425bIY9JnhFmMM= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=HPD66hky; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="HPD66hky" Received: by smtp.kernel.org (Postfix) with ESMTPSA id B3627C4CEDE; Thu, 26 Dec 2024 22:39:11 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1735252753; bh=zzHpg02nt2xCzx11z3qrPTPt9BM7ACn4sX/GXztIxTA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=HPD66hkyp6ULiLZXVVRtebU8omymUvvQ5tyb6NNu7Zjb5rPsoV6+LqUPyqKMV9BDY WBb8rplUSniQ5Zt54PRmW6ALOmYx71t45dHQXeaCE5rvRvkMfK7u0G3tnKcnVUN7Id etXoVXDg4Kaf+oyoLL63VV8xaiFmkQ+ZXNNf2hVquXpv6ZkJz2tMVzPaInDYMWzF3T Gc1vluxcP3Pf6PEj0nu3INYMdT6m6vQ3yOqYFbDNgGKMyr+cvmLIaDdu/ahA4Y7pkd VtK5LVAQ10OBgT3d8SixJ0Et575CCX6+iOhxZtzKobdLJAHDMs/Fxg1HuVZk5NGoEp g77FEx4NghSzw== From: Bjorn Andersson To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , Rob Herring , Krzysztof Kozlowski , Conor Dooley , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio , Richard Acayan Cc: Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter Subject: Re: (subset) [PATCH v2 0/4] drm/msm/adreno: Add A615 GPU for SDM670 and Pixel 3a Date: Thu, 26 Dec 2024 16:38:42 -0600 Message-ID: <173525273245.1449028.4895991910861314242.b4-ty@kernel.org> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20240806214452.16406-7-mailingradian@gmail.com> References: <20240806214452.16406-7-mailingradian@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 8bit On Tue, 06 Aug 2024 17:44:54 -0400, Richard Acayan wrote: > This adds support for the speed-binned A615 GPU on SDM670. > > Changes since v1 (20240730013844.41951-6-mailingradian@gmail.com): > - add Acked-by tag (1/4) > - add OPPs exclusive to some speed bins (3/4) > - enable GMU by default (3/4) > > [...] Applied, thanks! [3/4] arm64: dts: qcom: sdm670: add gpu commit: cd89483a1327c0317a655cca1daf9521c7ec7529 [4/4] arm64: dts: qcom: sdm670-google-sargo: enable gpu commit: fbf7cfa3ea986e5bf426748aa8afa386df61456f Best regards, -- Bjorn Andersson