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From: "Rob Herring (Arm)" <robh@kernel.org>
To: niravkumar.l.rabara@intel.com
Cc: Conor Dooley <conor+dt@kernel.org>,
	Dinh Nguyen <dinguyen@kernel.org>,
	 devicetree@vger.kernel.org,
	Krzysztof Kozlowski <krzk+dt@kernel.org>,
	 linux-kernel@vger.kernel.org
Subject: Re: [PATCH] arm64: dts: socfpga: agilex5: add qspi flash node
Date: Wed, 08 Jan 2025 08:22:12 -0600	[thread overview]
Message-ID: <173634584266.4189204.11167110536681373948.robh@kernel.org> (raw)
In-Reply-To: <20250108112834.2880709-1-niravkumar.l.rabara@intel.com>


On Wed, 08 Jan 2025 19:28:34 +0800, niravkumar.l.rabara@intel.com wrote:
> From: Niravkumar L Rabara <niravkumar.l.rabara@intel.com>
> 
> Add Micron qspi nor flash node for Intel SoCFPGA Agilex5.
> 
> Signed-off-by: Niravkumar L Rabara <niravkumar.l.rabara@intel.com>
> ---
>  .../boot/dts/intel/socfpga_agilex5_socdk.dts  | 33 +++++++++++++++++++
>  1 file changed, 33 insertions(+)
> 


My bot found new DTB warnings on the .dts files added or changed in this
series.

Some warnings may be from an existing SoC .dtsi. Or perhaps the warnings
are fixed by another series. Ultimately, it is up to the platform
maintainer whether these warnings are acceptable or not. No need to reply
unless the platform maintainer has comments.

If you already ran DT checks and didn't see these error(s), then
make sure dt-schema is up to date:

  pip3 install dtschema --upgrade


New warnings running 'make CHECK_DTBS=y intel/socfpga_agilex5_socdk.dtb' for 20250108112834.2880709-1-niravkumar.l.rabara@intel.com:

arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dtb: flash@0: Unevaluated properties are not allowed ('cdns,block-size', 'cdns,page-size' were unexpected)
	from schema $id: http://devicetree.org/schemas/mtd/jedec,spi-nor.yaml#






      parent reply	other threads:[~2025-01-08 14:22 UTC|newest]

Thread overview: 3+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-01-08 11:28 niravkumar.l.rabara
2025-01-08 11:49 ` Krzysztof Kozlowski
2025-01-08 14:22 ` Rob Herring (Arm) [this message]

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