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From: Sean Christopherson <seanjc@google.com>
To: Sean Christopherson <seanjc@google.com>,
	Paolo Bonzini <pbonzini@redhat.com>
Cc: kvm@vger.kernel.org, linux-kernel@vger.kernel.org,
	 Maxim Levitsky <mlevitsk@redhat.com>
Subject: Re: [PATCH] KVM: selftests: Use data load to trigger LLC references/misses in Intel PMU
Date: Thu,  9 Jan 2025 11:47:17 -0800	[thread overview]
Message-ID: <173645118101.885497.8247079551108053264.b4-ty@google.com> (raw)
In-Reply-To: <20241127235627.4049619-1-seanjc@google.com>

On Wed, 27 Nov 2024 15:56:27 -0800, Sean Christopherson wrote:
> In the PMU counters test, add a data load in the measured loop and target
> the data with CLFLUSH{OPT} in order to (try to) guarantee the loop
> generates LLC misses and fills.  Per the SDM, some hardware prefetchers
> are allowed to omit relevant PMU events, and Emerald Rapids (and possibly
> Sapphire Rapids) appears to have gained an instruction prefetcher that
> bypasses event counts.  E.g. the test will consistently fail on EMR CPUs,
> but then pass with seemingly benign changes to the code.
> 
> [...]

Applied to kvm-x86 selftests, thanks!

[1/1] KVM: selftests: Use data load to trigger LLC references/misses in Intel PMU
      https://github.com/kvm-x86/linux/commit/7803339fa929

--
https://github.com/kvm-x86/linux/tree/next

      reply	other threads:[~2025-01-09 19:48 UTC|newest]

Thread overview: 2+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-11-27 23:56 Sean Christopherson
2025-01-09 19:47 ` Sean Christopherson [this message]

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