From: "Rob Herring (Arm)" <robh@kernel.org>
To: Atish Patra <atishp@rivosinc.com>
Cc: Namhyung Kim <namhyung@kernel.org>,
linux-arm-kernel@lists.infradead.org,
Peter Zijlstra <peterz@infradead.org>,
Mark Rutland <mark.rutland@arm.com>,
linux-riscv@lists.infradead.org, weilin.wang@intel.com,
Will Deacon <will@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Anup Patel <anup@brainfault.org>,
Alexander Shishkin <alexander.shishkin@linux.intel.com>,
Jiri Olsa <jolsa@kernel.org>,
Adrian Hunter <adrian.hunter@intel.com>,
Ingo Molnar <mingo@redhat.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Ian Rogers <irogers@google.com>,
linux-perf-users@vger.kernel.org,
Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@sifive.com>,
Conor Dooley <conor@kernel.org>,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
Conor Dooley <conor+dt@kernel.org>,
Atish Patra <atishp@atishpatra.org>,
kvm@vger.kernel.org, Arnaldo Carvalho de Melo <acme@kernel.org>,
kvm-riscv@lists.infradead.org
Subject: Re: [PATCH v2 10/21] dt-bindings: riscv: add Smcntrpmf ISA extension description
Date: Tue, 14 Jan 2025 18:57:33 -0600 [thread overview]
Message-ID: <173690265103.2069740.11443232308035656965.robh@kernel.org> (raw)
In-Reply-To: <20250114-counter_delegation-v2-10-8ba74cdb851b@rivosinc.com>
On Tue, 14 Jan 2025 14:57:35 -0800, Atish Patra wrote:
> Add the description for Smcntrpmf ISA extension
>
> Signed-off-by: Atish Patra <atishp@rivosinc.com>
> ---
> Documentation/devicetree/bindings/riscv/extensions.yaml | 7 +++++++
> 1 file changed, 7 insertions(+)
>
My bot found errors running 'make dt_binding_check' on your patch:
yamllint warnings/errors:
dtschema/dtc warnings/errors:
doc reference errors (make refcheckdocs):
See https://patchwork.ozlabs.org/project/devicetree-bindings/patch/20250114-counter_delegation-v2-10-8ba74cdb851b@rivosinc.com
The base for the series is generally the latest rc1. A different dependency
should be noted in *this* patch.
If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:
pip3 install dtschema --upgrade
Please check and re-submit after running the above command yourself. Note
that DT_SCHEMA_FILES can be set to your schema file to speed up checking
your schema. However, it must be unset to test all examples with your schema.
next prev parent reply other threads:[~2025-01-15 0:57 UTC|newest]
Thread overview: 25+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-01-14 22:57 [PATCH v2 00/21] Add Counter delegation ISA extension support Atish Patra
2025-01-14 22:57 ` [PATCH v2 01/21] perf pmu-events: Add functions in jevent.py to parse counter and event info for hardware aware grouping Atish Patra
2025-01-14 22:57 ` [PATCH v2 02/21] RISC-V: Add Sxcsrind ISA extension CSR definitions Atish Patra
2025-01-14 22:57 ` [PATCH v2 03/21] RISC-V: Add Sxcsrind ISA extension definition and parsing Atish Patra
2025-01-14 22:57 ` [PATCH v2 04/21] dt-bindings: riscv: add Sxcsrind ISA extension description Atish Patra
2025-01-15 0:57 ` Rob Herring (Arm)
2025-01-14 22:57 ` [PATCH v2 05/21] RISC-V: Define indirect CSR access helpers Atish Patra
2025-01-14 22:57 ` [PATCH v2 06/21] RISC-V: Add Sscfg extension CSR definition Atish Patra
2025-01-14 22:57 ` [PATCH v2 07/21] RISC-V: Add Ssccfg ISA extension definition and parsing Atish Patra
2025-01-14 22:57 ` [PATCH v2 08/21] dt-bindings: riscv: add Ssccfg ISA extension description Atish Patra
2025-01-15 0:57 ` Rob Herring (Arm)
2025-01-14 22:57 ` [PATCH v2 09/21] RISC-V: Add Smcntrpmf extension parsing Atish Patra
2025-01-14 22:57 ` [PATCH v2 10/21] dt-bindings: riscv: add Smcntrpmf ISA extension description Atish Patra
2025-01-15 0:57 ` Rob Herring (Arm) [this message]
2025-01-14 22:57 ` [PATCH v2 11/21] RISC-V: perf: Restructure the SBI PMU code Atish Patra
2025-01-14 22:57 ` [PATCH v2 12/21] RISC-V: perf: Modify the counter discovery mechanism Atish Patra
2025-01-14 22:57 ` [PATCH v2 13/21] RISC-V: perf: Add a mechanism to defined legacy event encoding Atish Patra
2025-01-14 22:57 ` [PATCH v2 14/21] RISC-V: perf: Implement supervisor counter delegation support Atish Patra
2025-01-14 22:57 ` [PATCH v2 15/21] RISC-V: perf: Skip PMU SBI extension when not implemented Atish Patra
2025-01-14 22:57 ` [PATCH v2 16/21] RISC-V: perf: Use config2/vendor table for event to counter mapping Atish Patra
2025-01-14 22:57 ` [PATCH v2 17/21] RISC-V: perf: Add legacy event encodings via sysfs Atish Patra
2025-01-14 22:57 ` [PATCH v2 18/21] RISC-V: perf: Add Qemu virt machine events Atish Patra
2025-01-14 22:57 ` [PATCH v2 19/21] tools/perf: Support event code for arch standard events Atish Patra
2025-01-14 22:57 ` [PATCH v2 20/21] tools/perf: Pass the Counter constraint values in the pmu events Atish Patra
2025-01-14 22:57 ` [PATCH v2 21/21] Sync empty-pmu-events.c with autogenerated one Atish Patra
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