Re: [Patch v2 6/7] perf/x86/intel: Fix intel_cap handling on hybrid PMUs

["Falcon, Thomas" <thomas.falcon@intel.com>]

On Mon, 2026-07-13 at 16:27 +0800, Dapeng Mi wrote:
> intel_cap (IA32_PERF_CAPABILITIES) updates are currently tied to
> X86_FEATURE_ARCH_PERFMON_EXT, but these are independent feature
> paths.
> As a result, hybrid PMU capability state can be updated under the
> wrong
> condition.
> 
> Also, intel_pmu_broken_perf_cap() is too narrow. Per RPL018, the
> missing
> PERF_METRICS_AVAILABLE bit affects both Raptor Lake and Meteor Lake
> parts, not only the currently covered subset.
> 
> Move intel_cap updates out of the ARCH_PERFMON_EXT-gated path, extend
> intel_pmu_broken_perf_cap() coverage to both RPL and MTL families,
> and
> introduce intel_update_pmu_caps() to centralize PMU capability
> updates.
> 
> Signed-off-by: Dapeng Mi <dapeng1.mi@linux.intel.com>
> ---
>  arch/x86/events/intel/core.c | 41 ++++++++++++++++++++++++++--------
> --
>  1 file changed, 30 insertions(+), 11 deletions(-)
> 
> diff --git a/arch/x86/events/intel/core.c
> b/arch/x86/events/intel/core.c
> index c418176065f6..bec92163a09f 100644
> --- a/arch/x86/events/intel/core.c
> +++ b/arch/x86/events/intel/core.c
> @@ -6147,8 +6147,15 @@ static void intel_pmu_check_extra_regs(struct
> extra_reg *extra_regs);
>  
>  static inline bool intel_pmu_broken_perf_cap(void)
>  {
> -	/* The Perf Metric (Bit 15) is always cleared */
> -	if (boot_cpu_data.x86_vfm == INTEL_METEORLAKE ||
> +	/*
> +	 * The Perf Metric (Bit 15) is always cleared on P-core of
> +	 * PRL and MTL. Details can be found in RPL018 Errata
> Details.

Typo here. Should be RPL.

Thanks,
Tom

> +	 *
> https://edc.intel.com/content/www/us/en/design/products/platforms/details/raptor-lake-s/13th-generation-core-processor-specification-update/errata-details/
> +	 */
> +	if (boot_cpu_data.x86_vfm == INTEL_RAPTORLAKE ||
> +	    boot_cpu_data.x86_vfm == INTEL_RAPTORLAKE_P ||
> +	    boot_cpu_data.x86_vfm == INTEL_RAPTORLAKE_S ||
> +	    boot_cpu_data.x86_vfm == INTEL_METEORLAKE ||
>  	    boot_cpu_data.x86_vfm == INTEL_METEORLAKE_L)
>  		return true;
>  
> @@ -6183,7 +6190,7 @@ static inline void
> __intel_update_large_pebs_flags(struct pmu *pmu)
>  
>  #define counter_mask(_gp, _fixed) ((_gp) | ((u64)(_fixed) <<
> INTEL_PMC_IDX_FIXED))
>  
> -static void update_pmu_cap(struct pmu *pmu)
> +static void update_pmu_cap_from_perfmonext(struct pmu *pmu)
>  {
>  	unsigned int eax, ebx, ecx, edx;
>  	union cpuid35_eax eax_0;
> @@ -6241,10 +6248,24 @@ static void update_pmu_cap(struct pmu *pmu)
>  		WARN_ON(x86_pmu.arch_pebs == 1);
>  		x86_pmu.arch_pebs = 0;
>  	}
> +}
> +
> +static void intel_update_pmu_caps(struct pmu *pmu)
> +{
> +	if (this_cpu_has(X86_FEATURE_ARCH_PERFMON_EXT))
> +		update_pmu_cap_from_perfmonext(pmu);
>  
> -	if (!intel_pmu_broken_perf_cap()) {
> -		/* Perf Metric (Bit 15) and PEBS via PT (Bit 16) are
> hybrid enumeration */
> -		rdmsrq(MSR_IA32_PERF_CAPABILITIES, hybrid(pmu,
> intel_cap).capabilities);
> +	if (is_hybrid() && this_cpu_has(X86_FEATURE_PDCM)) {
> +		rdmsrq(MSR_IA32_PERF_CAPABILITIES,
> +		       hybrid(pmu, intel_cap).capabilities);
> +
> +		/*
> +		 * Restore perf_metrics on platforms with broken
> +		 * perf_capablities.
> +		 */
> +		if (intel_pmu_broken_perf_cap() &&
> +		    hybrid_pmu(pmu)->pmu_type == hybrid_big)
> +			hybrid(pmu, intel_cap).perf_metrics = 1;
>  	}
>  }
>  
> @@ -6329,9 +6350,7 @@ static bool init_hybrid_pmu(int cpu)
>  	if (!cpumask_empty(&pmu->supported_cpus))
>  		goto end;
>  
> -	if (this_cpu_has(X86_FEATURE_ARCH_PERFMON_EXT))
> -		update_pmu_cap(&pmu->pmu);
> -
> +	intel_update_pmu_caps(&pmu->pmu);
>  	intel_pmu_check_hybrid_pmus(pmu);
>  
>  	if (!check_hw_exists(pmu->cntr_mask, pmu->fixed_cntr_mask))
> {
> @@ -8828,8 +8847,8 @@ __init int intel_pmu_init(void)
>  	 * from the leaf 0xa. The core specific update will be done
> later
>  	 * when a new type is online.
>  	 */
> -	if (!is_hybrid() &&
> boot_cpu_has(X86_FEATURE_ARCH_PERFMON_EXT))
> -		update_pmu_cap(NULL);
> +	if (!is_hybrid())
> +		intel_update_pmu_caps(NULL);
>  
>  	if (x86_pmu.arch_pebs) {
>  		static_call_update(intel_pmu_disable_event_ext,