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From: "tip-bot2 for Ahmed S. Darwish" <tip-bot2@linutronix.de>
To: linux-tip-commits@vger.kernel.org
Cc: Ingo Molnar <mingo@kernel.org>,
	Thomas Gleixner <tglx@linutronix.de>,
	"Ahmed S. Darwish" <darwi@linutronix.de>,
	"H. Peter Anvin" <hpa@zytor.com>,
	Linus Torvalds <torvalds@linux-foundation.org>,
	x86@kernel.org, linux-kernel@vger.kernel.org
Subject: [tip: x86/cpu] x86/cacheinfo: Remove CPUID leaf 0x2 parsing loop
Date: Tue, 25 Mar 2025 09:36:36 -0000	[thread overview]
Message-ID: <174289539647.14745.12398405425285372043.tip-bot2@tip-bot2> (raw)
In-Reply-To: <20250324133324.23458-3-darwi@linutronix.de>

The following commit has been merged into the x86/cpu branch of tip:

Commit-ID:     09a1da4beb310420b720994f7b6599e8d0bce3e1
Gitweb:        https://git.kernel.org/tip/09a1da4beb310420b720994f7b6599e8d0bce3e1
Author:        Ahmed S. Darwish <darwi@linutronix.de>
AuthorDate:    Mon, 24 Mar 2025 14:32:57 +01:00
Committer:     Ingo Molnar <mingo@kernel.org>
CommitterDate: Tue, 25 Mar 2025 10:22:02 +01:00

x86/cacheinfo: Remove CPUID leaf 0x2 parsing loop

Leaf 0x2 output includes a "query count" byte where it was supposed to
specify the number of repeated CPUID leaf 0x2 subleaf 0 queries needed to
extract all of the CPU's cache and TLB descriptors.

Per current Intel manuals, all CPUs supporting this leaf "will always"
return an iteration count of 1.

Remove the leaf 0x2 query loop and just query the hardware once.

Note, as previously done at commit aec28d852ed2 ("x86/cpuid: Standardize
on u32 in <asm/cpuid/api.h>"), standardize on using 'u32' and 'u8' types.

Suggested-by: Ingo Molnar <mingo@kernel.org>
Suggested-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Ahmed S. Darwish <darwi@linutronix.de>
Signed-off-by: Ingo Molnar <mingo@kernel.org>
Cc: H. Peter Anvin <hpa@zytor.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Link: https://lore.kernel.org/r/20250324133324.23458-3-darwi@linutronix.de
---
 arch/x86/kernel/cpu/cacheinfo.c | 77 +++++++++++++++-----------------
 1 file changed, 37 insertions(+), 40 deletions(-)

diff --git a/arch/x86/kernel/cpu/cacheinfo.c b/arch/x86/kernel/cpu/cacheinfo.c
index b3a5209..36782fd 100644
--- a/arch/x86/kernel/cpu/cacheinfo.c
+++ b/arch/x86/kernel/cpu/cacheinfo.c
@@ -42,7 +42,7 @@ static cpumask_var_t cpu_cacheinfo_mask;
 unsigned int memory_caching_control __ro_after_init;
 
 struct _cache_table {
-	unsigned char descriptor;
+	u8 descriptor;
 	char cache_type;
 	short size;
 };
@@ -783,50 +783,47 @@ void init_intel_cacheinfo(struct cpuinfo_x86 *c)
 
 	/* Don't use CPUID(2) if CPUID(4) is supported. */
 	if (!ci->num_leaves && c->cpuid_level > 1) {
-		/* supports eax=2  call */
-		int j, n;
-		unsigned int regs[4];
-		unsigned char *dp = (unsigned char *)regs;
-
-		/* Number of times to iterate */
-		n = cpuid_eax(2) & 0xFF;
-
-		for (i = 0 ; i < n ; i++) {
-			cpuid(2, &regs[0], &regs[1], &regs[2], &regs[3]);
-
-			/* If bit 31 is set, this is an unknown format */
-			for (j = 0 ; j < 4 ; j++)
-				if (regs[j] & (1 << 31))
-					regs[j] = 0;
-
-			/* Byte 0 is level count, not a descriptor */
-			for (j = 1 ; j < 16 ; j++) {
-				unsigned char des = dp[j];
-				unsigned char k = 0;
-
-				/* look up this descriptor in the table */
-				while (cache_table[k].descriptor != 0) {
-					if (cache_table[k].descriptor == des) {
-						switch (cache_table[k].cache_type) {
-						case LVL_1_INST:
-							l1i += cache_table[k].size;
-							break;
-						case LVL_1_DATA:
-							l1d += cache_table[k].size;
-							break;
-						case LVL_2:
-							l2 += cache_table[k].size;
-							break;
-						case LVL_3:
-							l3 += cache_table[k].size;
-							break;
-						}
+		u32 regs[4];
+		u8 *desc = (u8 *)regs;
 
+		cpuid(2, &regs[0], &regs[1], &regs[2], &regs[3]);
+
+		/* Intel CPUs must report an iteration count of 1 */
+		if (desc[0] != 0x01)
+			return;
+
+		/* If a register's bit 31 is set, it is an unknown format */
+		for (int i = 0; i < 4; i++) {
+			if (regs[i] & (1 << 31))
+				regs[i] = 0;
+		}
+
+		/* Skip the first byte as it is not a descriptor */
+		for (int i = 1; i < 16; i++) {
+			u8 des = desc[i];
+			u8 k = 0;
+
+			/* look up this descriptor in the table */
+			while (cache_table[k].descriptor != 0) {
+				if (cache_table[k].descriptor == des) {
+					switch (cache_table[k].cache_type) {
+					case LVL_1_INST:
+						l1i += cache_table[k].size;
+						break;
+					case LVL_1_DATA:
+						l1d += cache_table[k].size;
+						break;
+					case LVL_2:
+						l2 += cache_table[k].size;
+						break;
+					case LVL_3:
+						l3 += cache_table[k].size;
 						break;
 					}
 
-					k++;
+					break;
 				}
+				k++;
 			}
 		}
 	}

  reply	other threads:[~2025-03-25  9:36 UTC|newest]

Thread overview: 59+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-03-24 13:32 [PATCH v4 00/29] x86: Leaf 0x2 and leaf 0x4 refactorings Ahmed S. Darwish
2025-03-24 13:32 ` [PATCH v4 01/29] x86/cpu: Remove leaf 0x2 parsing loop Ahmed S. Darwish
2025-03-25  9:36   ` [tip: x86/cpu] x86/cpu: Remove CPUID " tip-bot2 for Ahmed S. Darwish
2025-03-24 13:32 ` [PATCH v4 02/29] x86/cacheinfo: Remove " Ahmed S. Darwish
2025-03-25  9:36   ` tip-bot2 for Ahmed S. Darwish [this message]
2025-03-24 13:32 ` [PATCH v4 03/29] x86/cpu: Introduce and use leaf 0x2 parsing helpers Ahmed S. Darwish
2025-03-25  9:36   ` [tip: x86/cpu] x86/cpu: Introduce and use CPUID " tip-bot2 for Ahmed S. Darwish
2025-03-24 13:32 ` [PATCH v4 04/29] x86/cacheinfo: Use " Ahmed S. Darwish
2025-03-25  9:36   ` [tip: x86/cpu] x86/cacheinfo: Use CPUID " tip-bot2 for Ahmed S. Darwish
2025-03-24 13:33 ` [PATCH v4 05/29] x86/cacheinfo: Refactor leaf 0x2 cache descriptor lookup Ahmed S. Darwish
2025-03-25  9:36   ` [tip: x86/cpu] x86/cacheinfo: Refactor CPUID " tip-bot2 for Thomas Gleixner
2025-03-24 13:33 ` [PATCH v4 06/29] x86/cacheinfo: Properly name amd_cpuid4()'s first parameter Ahmed S. Darwish
2025-03-25  9:36   ` [tip: x86/cpu] " tip-bot2 for Thomas Gleixner
2025-03-24 13:33 ` [PATCH v4 07/29] x86/cacheinfo: Use proper name for cacheinfo instances Ahmed S. Darwish
2025-03-25  9:36   ` [tip: x86/cpu] " tip-bot2 for Thomas Gleixner
2025-03-24 13:33 ` [PATCH v4 08/29] x86/cacheinfo: Constify _cpuid4_info_regs instances Ahmed S. Darwish
2025-03-25  9:36   ` [tip: x86/cpu] " tip-bot2 for Ahmed S. Darwish
2025-03-24 13:33 ` [PATCH v4 09/29] x86/cacheinfo: Align ci_info_init() assignment expressions Ahmed S. Darwish
2025-03-25  9:36   ` [tip: x86/cpu] " tip-bot2 for Ahmed S. Darwish
2025-03-24 13:33 ` [PATCH v4 10/29] x86/cacheinfo: Standardize _cpuid4_info_regs instance naming Ahmed S. Darwish
2025-03-25  9:36   ` [tip: x86/cpu] " tip-bot2 for Ahmed S. Darwish
2025-03-24 13:33 ` [PATCH v4 11/29] x86/cacheinfo: Consolidate AMD/Hygon leaf 0x8000001d calls Ahmed S. Darwish
2025-03-25  9:36   ` [tip: x86/cpu] " tip-bot2 for Ahmed S. Darwish
2025-03-24 13:33 ` [PATCH v4 12/29] x86/cacheinfo: Separate amd_northbridge from _cpuid4_info_regs Ahmed S. Darwish
2025-03-25  9:36   ` [tip: x86/cpu] " tip-bot2 for Ahmed S. Darwish
2025-03-24 13:33 ` [PATCH v4 13/29] x86/cacheinfo: Move AMD cache_disable_0/1 handling to separate file Ahmed S. Darwish
2025-03-25  9:36   ` [tip: x86/cpu] " tip-bot2 for Ahmed S. Darwish
2025-03-24 13:33 ` [PATCH v4 14/29] x86/cacheinfo: Use sysfs_emit() for sysfs attributes show() Ahmed S. Darwish
2025-03-25  9:36   ` [tip: x86/cpu] " tip-bot2 for Ahmed S. Darwish
2025-03-24 13:33 ` [PATCH v4 15/29] x86/cacheinfo: Separate Intel and AMD leaf 0x4 code paths Ahmed S. Darwish
2025-03-25  9:36   ` [tip: x86/cpu] x86/cacheinfo: Separate Intel and AMD CPUID " tip-bot2 for Ahmed S. Darwish
2025-03-24 13:33 ` [PATCH v4 16/29] x86/cacheinfo: Rename _cpuid4_info_regs to _cpuid4_info Ahmed S. Darwish
2025-03-25  9:36   ` [tip: x86/cpu] x86/cacheinfo: Rename 'struct _cpuid4_info_regs' to 'struct _cpuid4_info' tip-bot2 for Ahmed S. Darwish
2025-03-24 13:33 ` [PATCH v4 17/29] x86/cacheinfo: Clarify type markers for leaf 0x2 cache descriptors Ahmed S. Darwish
2025-03-25  9:36   ` [tip: x86/cpu] x86/cacheinfo: Clarify type markers for CPUID " tip-bot2 for Ahmed S. Darwish
2025-03-24 13:33 ` [PATCH v4 18/29] x86/cacheinfo: Use enums for cache descriptor types Ahmed S. Darwish
2025-03-25  9:36   ` [tip: x86/cpu] " tip-bot2 for Ahmed S. Darwish
2025-03-24 13:33 ` [PATCH v4 19/29] x86/cpu: Use enums for TLB " Ahmed S. Darwish
2025-03-25  9:36   ` [tip: x86/cpu] " tip-bot2 for Ahmed S. Darwish
2025-03-24 13:33 ` [PATCH v4 20/29] x86/cpu: Consolidate CPUID leaf 0x2 tables Ahmed S. Darwish
2025-03-25  9:36   ` [tip: x86/cpu] " tip-bot2 for Thomas Gleixner
2025-03-24 13:33 ` [PATCH v4 21/29] x86/cacheinfo: Use consolidated leaf 0x2 descriptor table Ahmed S. Darwish
2025-03-25  9:36   ` [tip: x86/cpu] x86/cacheinfo: Use consolidated CPUID " tip-bot2 for Ahmed S. Darwish
2025-03-24 13:33 ` [PATCH v4 22/29] x86/cpu: Use consolidated " Ahmed S. Darwish
2025-03-25  9:36   ` [tip: x86/cpu] x86/cpu: Use consolidated CPUID " tip-bot2 for Ahmed S. Darwish
2025-03-24 13:33 ` [PATCH v4 23/29] x86/cacheinfo: Separate leaf 0x2 handling and post-processing logic Ahmed S. Darwish
2025-03-25  9:36   ` [tip: x86/cpu] x86/cacheinfo: Separate CPUID " tip-bot2 for Ahmed S. Darwish
2025-03-24 13:33 ` [PATCH v4 24/29] x86/cacheinfo: Separate Intel leaf 0x4 handling Ahmed S. Darwish
2025-03-25  9:36   ` [tip: x86/cpu] x86/cacheinfo: Separate Intel CPUID " tip-bot2 for Ahmed S. Darwish
2025-03-24 13:33 ` [PATCH v4 25/29] x86/cacheinfo: Extract out cache level topology ID calculation Ahmed S. Darwish
2025-03-25  9:36   ` [tip: x86/cpu] " tip-bot2 for Ahmed S. Darwish
2025-03-24 13:33 ` [PATCH v4 26/29] x86/cacheinfo: Extract out cache self-snoop checks Ahmed S. Darwish
2025-03-25  9:36   ` [tip: x86/cpu] " tip-bot2 for Ahmed S. Darwish
2025-03-24 13:33 ` [PATCH v4 27/29] x86/cacheinfo: Relocate leaf 0x4 cache_type mapping Ahmed S. Darwish
2025-03-25  9:36   ` [tip: x86/cpu] x86/cacheinfo: Relocate CPUID " tip-bot2 for Ahmed S. Darwish
2025-03-24 13:33 ` [PATCH v4 28/29] x86/cacheinfo: Introduce cpuid_amd_hygon_has_l3_cache() Ahmed S. Darwish
2025-03-25  9:36   ` [tip: x86/cpu] " tip-bot2 for Ahmed S. Darwish
2025-03-24 13:33 ` [PATCH v4 29/29] x86/cacheinfo: Apply maintainer-tip coding style fixes Ahmed S. Darwish
2025-03-25  9:36   ` [tip: x86/cpu] " tip-bot2 for Ahmed S. Darwish

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