From: patchwork-bot+linux-riscv@kernel.org
To: Alexandre Ghiti <alexghiti@rivosinc.com>
Cc: linux-riscv@lists.infradead.org, paul.walmsley@sifive.com,
palmer@dabbelt.com, aou@eecs.berkeley.edu, alex@ghiti.fr,
cyrilbur@tenstorrent.com, andybnac@gmail.com, debug@rivosinc.com,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH v2] riscv: uaccess: Only restore the CSR_STATUS SUM bit
Date: Thu, 05 Jun 2025 01:30:32 +0000 [thread overview]
Message-ID: <174908703299.2529829.8532733312132179877.git-patchwork-notify@kernel.org> (raw)
In-Reply-To: <20250602121543.1544278-1-alexghiti@rivosinc.com>
Hello:
This patch was applied to riscv/linux.git (for-next)
by Palmer Dabbelt <palmer@dabbelt.com>:
On Mon, 2 Jun 2025 12:15:43 +0000 you wrote:
> From: Cyril Bur <cyrilbur@tenstorrent.com>
>
> During switch to csrs will OR the value of the register into the
> corresponding csr. In this case we're only interested in restoring the
> SUM bit not the entire register.
>
> Fixes: 788aa64c0c01 ("riscv: save the SR_SUM status over switches")
> Signed-off-by: Cyril Bur <cyrilbur@tenstorrent.com>
> Link: https://lore.kernel.org/r/20250522160954.429333-1-cyrilbur@tenstorrent.com
> Co-developed-by: Alexandre Ghiti <alexghiti@rivosinc.com>
> Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com>
>
> [...]
Here is the summary with links:
- [v2] riscv: uaccess: Only restore the CSR_STATUS SUM bit
https://git.kernel.org/riscv/c/4e27ce58e7fa
You are awesome, thank you!
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prev parent reply other threads:[~2025-06-05 1:30 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-06-02 12:15 Alexandre Ghiti
2025-06-05 1:30 ` patchwork-bot+linux-riscv [this message]
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