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From: Marc Zyngier <maz@kernel.org>
To: linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev,
	linux-kernel@vger.kernel.org,
	Wei-Lin Chang <r09922117@csie.ntu.edu.tw>
Cc: Oliver Upton <oliver.upton@linux.dev>,
	Joey Gouly <joey.gouly@arm.com>,
	Suzuki K Poulose <suzuki.poulose@arm.com>,
	Zenghui Yu <yuzenghui@huawei.com>,
	Catalin Marinas <catalin.marinas@arm.com>,
	Will Deacon <will@kernel.org>,
	Jintack Lim <jintack@cs.columbia.edu>,
	Christoffer Dall <christoffer.dall@arm.com>
Subject: Re: [PATCH] KVM: arm64: nv: Fix MI line level calculation in vgic_v3_nested_update_mi()
Date: Thu, 26 Jun 2025 08:52:50 +0100	[thread overview]
Message-ID: <175092436132.7925.6436811848886215951.b4-ty@kernel.org> (raw)
In-Reply-To: <20250625084709.3968844-1-r09922117@csie.ntu.edu.tw>

On Wed, 25 Jun 2025 16:47:09 +0800, Wei-Lin Chang wrote:
> The state of the vcpu's MI line should be asserted when its
> ICH_HCR_EL2.En is set and ICH_MISR_EL2 is non-zero. Using bitwise AND
> (&=) directly for this calculation will not give us the correct result
> when the LSB of the vcpu's ICH_MISR_EL2 isn't set. Correct this by first
> adjusting the return value of vgic_v3_get_misr() into 1 if it is
> non-zero.
> 
> [...]

Applied to fixes, thanks!

[1/1] KVM: arm64: nv: Fix MI line level calculation in vgic_v3_nested_update_mi()
      commit: af040a9a296044fd4b748786c2516f172a7617f1

Cheers,

	M.
-- 
Without deviation from the norm, progress is not possible.



      parent reply	other threads:[~2025-06-26  7:52 UTC|newest]

Thread overview: 4+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-06-25  8:47 Wei-Lin Chang
2025-06-25 16:45 ` Marc Zyngier
2025-06-26  5:57   ` Wei-Lin Chang
2025-06-26  7:52 ` Marc Zyngier [this message]

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