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Fri, 27 Jun 2025 16:32:05 -0700 (PDT) From: Inochi Amaoto To: Philipp Zabel , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen Wang , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Alexander Sverdlin , Yixun Lan , Ze Huang , Thomas Bonnefille , Inochi Amaoto Cc: devicetree@vger.kernel.org, sophgo@lists.linux.dev, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, Longbin Li Subject: Re: (subset) [PATCH v4 0/4] riscv: sophgo: cv18xx: Add reset generator support Date: Sat, 28 Jun 2025 07:31:50 +0800 Message-ID: <175106708298.79260.10445943203117657356.b4-ty@gmail.com> X-Mailer: git-send-email 2.50.0 In-Reply-To: <20250617070144.1149926-1-inochiama@gmail.com> References: <20250617070144.1149926-1-inochiama@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 8bit On Tue, 17 Jun 2025 15:01:38 +0800, Inochi Amaoto wrote: > Like SG2042, CV1800 Series SoCs also have simple bit reset generator. > Add necessary code and bindings for it. > > Changes from v4: > 1. patch 1: convert the compatible as entry of enum. > 1. patch 2, 3: apply Alexander's tag. > 1. patch 3: apply Junhui's tag. > > [...] Applied to for-next, thanks! [3/4] riscv: dts: sophgo: add reset generator for Sophgo CV1800 series SoC https://github.com/sophgo/linux/commit/fcb3f47c81afe43b336bf8033234417445789807 [4/4] riscv: dts: sophgo: add reset configuration for Sophgo CV1800 series SoC https://github.com/sophgo/linux/commit/880f18ee6772d4add69519cb7de2fcf9f4769cd6 Thanks, Inochi