Re: [PATCH v2] dt-bindings: interrupt-controller: Add missing Xilinx INTC binding

["Rob Herring (Arm)" <robh@kernel.org>]

On Thu, 24 Jul 2025 12:57:57 +0200, Michal Simek wrote:
> Add missing description for AMD/Xilinx interrupt controller. The binding is
> used by Microblaze before dt-binding even existed but never been
> documented properly.
> 
> IP acts as primary interrupt controller on Microblaze systems or can be
> used as secondary interrupt controller on ARM based systems like Zynq,
> ZynqMP, Versal or Versal Gen 2. Also as secondary interrupt controller on
> Microblaze-V (Risc-V) systems.
> 
> Over the years IP exists in multiple variants based on attached bus as OPB,
> PLB or AXI that's why generic filename is used.
> 
> Property xlnx,kind-of-intr is in hex because every bit position corresponds
> to interrupt line. Controller support mixing edge or level interrupts
> together and this is the property which distinguish them.
> 
> Signed-off-by: Michal Simek <michal.simek@amd.com>
> ---
> 
> Changes in v2:
> - update subject and commit message
> - drop second example
> 
> https://docs.amd.com/v/u/en-US/pg099-axi-intc
> 
> ---
>  .../interrupt-controller/xlnx,intc.yaml       | 82 +++++++++++++++++++
>  1 file changed, 82 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/interrupt-controller/xlnx,intc.yaml
> 

Applied, thanks!