From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1763339AbbA3V4E (ORCPT ); Fri, 30 Jan 2015 16:56:04 -0500 Received: from mout.kundenserver.de ([212.227.126.130]:49760 "EHLO mout.kundenserver.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754852AbbA3V4C (ORCPT ); Fri, 30 Jan 2015 16:56:02 -0500 From: Arnd Bergmann To: Joerg Roedel Cc: Will Deacon , Mitchel Humpherys , joro@8bytes.org, linux-arm-kernel@lists.infradead.org, iommu@lists.linux-foundation.org, linux-kernel@vger.kernel.org Subject: [PATCH] iommu: arm-smmu: avoid build warning Date: Fri, 30 Jan 2015 22:55:55 +0100 Message-ID: <1754709.y30A9Ie4hF@wuerfel> User-Agent: KMail/4.11.5 (Linux/3.16.0-10-generic; KDE/4.11.5; x86_64; ; ) MIME-Version: 1.0 Content-Transfer-Encoding: 7Bit Content-Type: text/plain; charset="us-ascii" X-Provags-ID: V03:K0:CuIOnopEqb9y24owGCJ+F7OWEHg05plttBqUKiHigfyNgfgwTY7 QXw3FYZan4AZb4z2aNGgzrLy/cjLTVEhTD1Xb+JIYBxukL0mm4P2NFSfC6medixBxEP9Tdj gGSDe9vo7Gn/glIRhSlJb+Cr/Sge7VP0xF6ROk9l4OTBzPnHlFGpXkMBJAjZQlojpvRgJFx PdkgJViZ2WUIBWjxQjK3g== X-UI-Out-Filterresults: notjunk:1; Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org ARM allmodconfig gained a new warning when dma_addr_t is 32-bit wide: drivers/iommu/arm-smmu.c: In function 'arm_smmu_iova_to_phys_hard': drivers/iommu/arm-smmu.c:1255:3: warning: right shift count >= width of type This changes the calculation so that the effective type is always 64-bit. Signed-off-by: Arnd Bergmann Fixes: 859a732e4f713 ("iommu/arm-smmu: add support for iova_to_phys through ATS1PR") diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c index 1d6d43bb3395..fc13dd56953e 100644 --- a/drivers/iommu/arm-smmu.c +++ b/drivers/iommu/arm-smmu.c @@ -1252,7 +1252,7 @@ static phys_addr_t arm_smmu_iova_to_phys_hard(struct iommu_domain *domain, } else { u32 reg = iova & ~0xfff; writel_relaxed(reg, cb_base + ARM_SMMU_CB_ATS1PR_LO); - reg = (iova & ~0xfff) >> 32; + reg = ((u64)iova & ~0xfff) >> 32; writel_relaxed(reg, cb_base + ARM_SMMU_CB_ATS1PR_HI); }