From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6CA242E2664; Tue, 12 Aug 2025 21:56:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755035800; cv=none; b=DFpIXxZDSA1UMA2JATIYPy1cVdyrqXrljLK237+VS/oS9etpq9ddtiQl8cnSe6tI6U9n7YCWMflhqfktk9Nczvm9wuNC9uT1SiDHSqI4uIHlrapuSdDGO/XnLtDMihnlajq2JyKKJGOl6UXQ2sjqK/60EbCqdnwyVQYDp3Zi2/U= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755035800; c=relaxed/simple; bh=VgXxxA2NG8Ilx12xVQPJsG3ZIK+2Y0VaQVCI/PW05JA=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=GJI/tJWwK1sWMMk2cQkUAtnEx9kCK8GKfdX/IYk+DTB3erxFtF3WhQZyzuL/RElRomXCP+DABBdH9uCKNEA/BYYAclIgkeeQUqhyR+jwSConKsqXSP5rR9zQTDw7cGFZS4bBMHuHE03bzyF99lOOpMYWilviQ1ZjxATYGIWQV3s= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=a/X2ApBG; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="a/X2ApBG" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 28C98C4CEFA; Tue, 12 Aug 2025 21:56:36 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1755035798; bh=VgXxxA2NG8Ilx12xVQPJsG3ZIK+2Y0VaQVCI/PW05JA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=a/X2ApBGlWSt/wUjFLkE827HNM4kEH6sJT6jzf2+DbfQ6oM3dy0rXjqWVZUksM7lS lh2oEmxSJT8p6yFq3g+yzPeIZTJY/qQfi5bgFuKBM8M6LBQ+WDlnIfkxYtwidI+Cle Wcp3c9X+zRTVNvpZjBpBphLwvAlyZp9glAMT+HEaqVMceQ2iDSr8dCd8NqwYcVPYIY WvDSR+T9HmeDaMmftRvDHlpr7GYWU5BHDkL0oDp0K51zYT8ntpzHCGfHZJn7cMZ9+H jmmj/Htb2u1Rpc6j5bdKG2aqtNVsK2HZ61OKUaEYgXhPkiNAVDDATfZkLpJ53hwvIU Q0pKm2BoOmz5g== From: Bjorn Andersson To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio , Catalin Marinas , Will Deacon , Taniya Das Cc: Ajit Pandey , Imran Shaik , Jagadeesh Kona , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Krzysztof Kozlowski , Bryan O'Donoghue , Konrad Dybcio , Dmitry Baryshkov , Dmitry Baryshkov Subject: Re: (subset) [PATCH v11 00/10] Add support for videocc, camcc, dispcc and gpucc on Qualcomm QCS615 platform Date: Tue, 12 Aug 2025 16:56:19 -0500 Message-ID: <175503322859.231048.11811110407884093606.b4-ty@kernel.org> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250702-qcs615-mm-v10-clock-controllers-v11-0-9c216e1615ab@quicinc.com> References: <20250702-qcs615-mm-v10-clock-controllers-v11-0-9c216e1615ab@quicinc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 8bit On Wed, 02 Jul 2025 14:34:20 +0530, Taniya Das wrote: > Add support for multimedia clock controllers on Qualcomm QCS615 platform. > Update the defconfig to enable these clock controllers. > > Changes in v11: > - Add a new reusable helper function to extract PLL_L_VAL, PLL_ALPHA_VAL and > PLL_USER_CTL / PLL_VCO_MASK [Dmitry] > - Add static to fix bot error in gpucc > - Link to v10: https://lore.kernel.org/r/20250625-qcs615-mm-v10-clock-controllers-v10-0-ec48255f90d8@quicinc.com > > [...] Applied, thanks! [10/10] arm64: defconfig: Enable QCS615 clock controllers commit: 4e4afd6bb9657d7cf23f6becf23706882b9822c0 Best regards, -- Bjorn Andersson