From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3DDB1242D6C; Sun, 24 Aug 2025 02:56:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756004176; cv=none; b=SeaLnaD+moxFjHa1CPwLdGYiNwfKNju540+D6J2Mz/aFblrd5LQnxUG69R5k+njM3VYmPNYmdCLmvKSkjTOeyKDObpFeGSAuhACaztofnKv86ESCJF91TB8PrUhmjEMmdoHSFMyuryZM9UPNXqbRlD3hsY2JuoFWUHchKbiF9tw= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756004176; c=relaxed/simple; bh=YoBQlm0ulSox3GmjDc721psnQpnF9RNfbeehuLeMArQ=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=RkkQOKFhsA9lLarMSEWHL8IP3U3a3aV/HJoPkQ85AfjA4VF1tJuSw2qlfGTlxBBe6vKMLdlzwSB7wqqpBrCQl6WHuEctKg91qOZwfgor55Id2wLJZVUVuz++mHZkOi7dikNPOI6rdfqBBF5t8mlyKCqgjfgJNNv3NT1Xxv4uIts= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=mp/L285J; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="mp/L285J" Received: by smtp.kernel.org (Postfix) with ESMTPSA id B9736C113D0; Sun, 24 Aug 2025 02:56:14 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1756004175; bh=YoBQlm0ulSox3GmjDc721psnQpnF9RNfbeehuLeMArQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=mp/L285JmYGRq+LCzcFVp1/DXEJ7HSy6Cc9KXQqpsziPWkWnNQLZK0qZxkfoWnhK2 9wMvO/Lbquii8jgBLvTHVP/m0MAmqD2m9rGUHynZmBz5TG+aUIHVk3+N3GL+WkAl9k YbZCC2+FzASNo6EHgrRystdht53vhg8kTBM6i01Wr86FHgWWfAxnWiD/4v/qb3fK27 m9R8D+DMEFJNvhkxCY7+30SKVPzfw7ls128wCD9LJLu9s79gWHW0k+jW8UWJqzPwwQ 3IHFZtBPS3/ynhQ4mqcdfzqmMeA8U9YnW+B5tKrTGlHTq+nEZCNxOiP0qNUp1SzFf5 B7gXsaqrkpr5g== From: Bjorn Andersson To: Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , "Rafael J. Wysocki" , Viresh Kumar , Manivannan Sadhasivam , Taniya Das Cc: Ajit Pandey , Imran Shaik , Jagadeesh Kona , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, Konrad Dybcio Subject: Re: (subset) [PATCH v5 0/3] Add support for clock controllers and CPU scaling for QCS615 Date: Sat, 23 Aug 2025 21:55:49 -0500 Message-ID: <175600415261.952266.11240532352802429049.b4-ty@kernel.org> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250702-qcs615-mm-cpu-dt-v4-v5-0-df24896cbb26@quicinc.com> References: <20250702-qcs615-mm-cpu-dt-v4-v5-0-df24896cbb26@quicinc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 8bit On Wed, 02 Jul 2025 14:43:08 +0530, Taniya Das wrote: > Add the video, camera, display and gpu clock controller nodes and the > cpufreq-hw node to support cpu scaling. > > Clock Dependency: > https://lore.kernel.org/all/20250702-qcs615-mm-v10-clock-controllers-v11-0-9c216e1615ab@quicinc.com > > Changes in v5: > - Update the documentation for CPUFREQ-HW for QCS615. > - Update the device tree node for cpufreq-hw to point to the new compatible. > - Link to v4: https://lore.kernel.org/r/20250625-qcs615-mm-cpu-dt-v4-v4-0-9ca880c53560@quicinc.com > > [...] Applied, thanks! [2/3] arm64: dts: qcom: qcs615: Add clock nodes for multimedia clock commit: f9c36698db91780eed4ee3a90794bda2a4252166 [3/3] arm64: dts: qcom: qcs615: Add CPU scaling clock node commit: fecc6e0b0260279cd1508903db62f370ef4530d4 Best regards, -- Bjorn Andersson