From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id ECEB621B9F1; Thu, 28 Aug 2025 14:26:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756391200; cv=none; b=FrR0qB/r8tgIYkICe4LZEiu8rPJYypKMkfaAieq2XAQHlf1QI3dbQCqwPikYwppPKETULJLcG9S7Gi7awq0i0MuQ1Ao4OydYyJSNrhR/NQVTW/UrKF06qhKmBvOHdQYxEQmC2GWhEQq/AyJ8+Oo6OQEkPau46ea+XW9yNbmOLGo= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756391200; c=relaxed/simple; bh=eJLj6KGnW/fcNI9Ld99rs+rSvaWSeJCbGunuVMEqCVY=; h=Date:Content-Type:MIME-Version:From:Cc:To:In-Reply-To:References: Message-Id:Subject; b=Dd/6TFgeCCdkzeic+x03ioQHbLIl47vhvqaxCPNUhsdvy78DeHgZVAlinIfwrALJlSyj7aay2ertBLCkXf8nmL38Qn4TTfIVF1KoDZd3K+hbbLD3J/C8c0wXGKi9hZDGK+M3pyejrTYjuOiqAqAcU5sSwopTjn8zanFdcoqLJIU= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=n7tzR99K; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="n7tzR99K" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 7085FC4CEED; Thu, 28 Aug 2025 14:26:39 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1756391199; bh=eJLj6KGnW/fcNI9Ld99rs+rSvaWSeJCbGunuVMEqCVY=; h=Date:From:Cc:To:In-Reply-To:References:Subject:From; b=n7tzR99KRMQSjLfO82sNklVWv3+11sgpF3dpnMZZzMG7QnfA0eMjkbhJhU9GbKUmz G3YHGZ8cHlKjowIOz2ScbElYUFyCEaIkd76j/ETGLZ5p7yxtYPdeUh4K6NAVlOz/1X EHmtoAWYjPHP1Asfx7E2KeEnNpWHWcSkml1uwXrtCD096KM7mz/NxJuFW0M7+JV2b9 zt7n2cRFNYJ72v96/EIZJYty0/JFqk2KfrUIxTEvndJNofkMGBvY+eCN9Kqav2Qfyx GJju+Rq1WfS2AEUjU3QPgagmqT65hecBrA7O9hVon4sfXRadstCJm1tsll2eoA3d1s OpFr53KHhyiTQ== Date: Thu, 28 Aug 2025 09:26:32 -0500 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 8bit Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: "Rob Herring (Arm)" Cc: Conor Dooley , linux-clk@vger.kernel.org, Michael Turquette , Philipp Zabel , Krzysztof Kozlowski , linux-tegra@vger.kernel.org, Jonathan Hunter , Thierry Reding , Stephen Boyd , Mikko Perttunen , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Prashant Gaikwad , Thierry Reding To: Svyatoslav Ryhel In-Reply-To: <20250828054403.7112-1-clamor95@gmail.com> References: <20250828054403.7112-1-clamor95@gmail.com> Message-Id: <175639108933.1621673.15061755256457797674.robh@kernel.org> Subject: Re: [PATCH v4 0/4] clk: tegra: add DFLL support for Tegra114 On Thu, 28 Aug 2025 08:43:59 +0300, Svyatoslav Ryhel wrote: > DFLL is a dedicated clock source for the Fast CPU. The DFLL is based on > a ring oscillator and translates voltage changes into frequency > compensation changes needed to prevent the CPU from failing and is > essential for correct CPU frequency scaling. > > --- > Changes in v2: > - dropped 'drivers:' from commit title > - aligned naming to Tegra114 > > Changes in v3: > - add DFLL support for Tegra 114 was split into dt header addition, > DFLL reset configuration and CVB tables implementation. > - added cleaner commit message to dt header commit > - added T210_ prefixes to Tegra210 CVB table macros > > Changes in v4: > - expanded commit message of car header adding commit > --- > > Svyatoslav Ryhel (4): > dt-bindings: reset: add Tegra114 car header > clk: tegra: add DFLL DVCO reset control for Tegra114 > clk: tegra: dfll: add CVB tables for Tegra114 > ARM: tegra: Add DFLL clock support for Tegra114 > > arch/arm/boot/dts/nvidia/tegra114.dtsi | 33 +++++ > drivers/clk/tegra/Kconfig | 2 +- > drivers/clk/tegra/clk-tegra114.c | 30 +++- > drivers/clk/tegra/clk-tegra124-dfll-fcpu.c | 158 +++++++++++++++++---- > drivers/clk/tegra/clk.h | 2 - > include/dt-bindings/reset/tegra114-car.h | 13 ++ > 6 files changed, 204 insertions(+), 34 deletions(-) > create mode 100644 include/dt-bindings/reset/tegra114-car.h > > -- > 2.48.1 > > > My bot found new DTB warnings on the .dts files added or changed in this series. Some warnings may be from an existing SoC .dtsi. Or perhaps the warnings are fixed by another series. Ultimately, it is up to the platform maintainer whether these warnings are acceptable or not. No need to reply unless the platform maintainer has comments. If you already ran DT checks and didn't see these error(s), then make sure dt-schema is up to date: pip3 install dtschema --upgrade This patch series was applied (using b4) to base: Base: attempting to guess base-commit... Base: tags/next-20250825 (best guess, 3/5 blobs matched) If this is not the correct base, please add 'base-commit' tag (or use b4 which does this automatically) New warnings running 'make CHECK_DTBS=y for arch/arm/boot/dts/nvidia/' for 20250828054403.7112-1-clamor95@gmail.com: arch/arm/boot/dts/nvidia/tegra114-tn7.dtb: /clock@70110000: failed to match any schema with compatible: ['nvidia,tegra114-dfll'] arch/arm/boot/dts/nvidia/tegra114-tn7.dtb: cpu@0 (arm,cortex-a15): 'operating-points' is a dependency of 'clock-latency' from schema $id: http://devicetree.org/schemas/arm/cpus.yaml# arch/arm/boot/dts/nvidia/tegra114-tn7.dtb: cpu@0 (arm,cortex-a15): Unevaluated properties are not allowed ('clock-latency' was unexpected) from schema $id: http://devicetree.org/schemas/arm/cpus.yaml# arch/arm/boot/dts/nvidia/tegra114-roth.dtb: /clock@70110000: failed to match any schema with compatible: ['nvidia,tegra114-dfll'] arch/arm/boot/dts/nvidia/tegra114-roth.dtb: cpu@0 (arm,cortex-a15): 'operating-points' is a dependency of 'clock-latency' from schema $id: http://devicetree.org/schemas/arm/cpus.yaml# arch/arm/boot/dts/nvidia/tegra114-roth.dtb: cpu@0 (arm,cortex-a15): Unevaluated properties are not allowed ('clock-latency' was unexpected) from schema $id: http://devicetree.org/schemas/arm/cpus.yaml# arch/arm/boot/dts/nvidia/tegra114-dalmore.dtb: /clock@70110000: failed to match any schema with compatible: ['nvidia,tegra114-dfll'] arch/arm/boot/dts/nvidia/tegra114-dalmore.dtb: cpu@0 (arm,cortex-a15): 'operating-points' is a dependency of 'clock-latency' from schema $id: http://devicetree.org/schemas/arm/cpus.yaml# arch/arm/boot/dts/nvidia/tegra114-dalmore.dtb: cpu@0 (arm,cortex-a15): Unevaluated properties are not allowed ('clock-latency' was unexpected) from schema $id: http://devicetree.org/schemas/arm/cpus.yaml# arch/arm/boot/dts/nvidia/tegra114-asus-tf701t.dtb: /clock@70110000: failed to match any schema with compatible: ['nvidia,tegra114-dfll'] arch/arm/boot/dts/nvidia/tegra114-asus-tf701t.dtb: cpu@0 (arm,cortex-a15): 'operating-points' is a dependency of 'clock-latency' from schema $id: http://devicetree.org/schemas/arm/cpus.yaml# arch/arm/boot/dts/nvidia/tegra114-asus-tf701t.dtb: cpu@0 (arm,cortex-a15): Unevaluated properties are not allowed ('clock-latency' was unexpected) from schema $id: http://devicetree.org/schemas/arm/cpus.yaml#