From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5924130CD87; Wed, 10 Sep 2025 15:14:56 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757517296; cv=none; b=BJ7EtfpetUqkIUJHR9+ZXVORFrDrvH6v6A5+eMtlYRg8ypC36wP5N3QC19/fMhjGG3U+a1kaZOcdBeWFHG4dq51jUAznrH4sQ+jNkkelmU7HvNbDVp++w/YlSbGewWy9lY25au9YxP6pItmJ089xAawdGer97ajARrBB+UR1USQ= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757517296; c=relaxed/simple; bh=2EMvJEZpAwWB3+UuDbsGNKSQvdZmA24xJU7MjldVB2g=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=bIGiSob9S7HJDlhftxakk9eRmLLvKSWOWUezcyASiKdzsQD0w4lGDeWYBwbL26YPzdqgeJujzEki4tIdyf20QJM5zirn19rZZJtTyNWeWhs/iEc5U1TXhskvXLezTA4dLWMRo417T30B20JdHypKJx3u1fi9mh5AD05Jj4H3+vY= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=WCFm1dAQ; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="WCFm1dAQ" Received: by smtp.kernel.org (Postfix) with ESMTPSA id B942DC4CEEB; Wed, 10 Sep 2025 15:14:55 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1757517295; bh=2EMvJEZpAwWB3+UuDbsGNKSQvdZmA24xJU7MjldVB2g=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=WCFm1dAQkMfoZupO9Abjy2cF1PCCIhpEpa1dTU8s4XFG8jM8AODO3ROtAJV3gpwpT n5QsFlb7329NMT7MrooZpJoTlgMwPEiSy+bfYpzvbXnoCnWu/2hNJYj2hO4pOpLJLg sfcklF2s4H3oxPa8JGSQ0UHnXYHTnv0LANXzqwa8OLuzttM/bJTlAhfwYpN7NxL9xk r/ysJaJEN3JeNTfGE7Py1567iIOTUOzFt2Ue+GlRLBcZn2s/sZXlhlCNweTkjDOC0H lnTTrC298ANwH8nVXNsFryMWlW0rYWrxqCa0pdPDUQExXxxdCd6jKfqHyVt19JiXkU KHpOyPtrPx5/A== Date: Wed, 10 Sep 2025 10:14:52 -0500 From: "Rob Herring (Arm)" To: Biju Cc: linux-kernel@vger.kernel.org, Biju Das , devicetree@vger.kernel.org, Conor Dooley , Uwe =?iso-8859-1?Q?Kleine-K=F6nig?= , Geert Uytterhoeven , Krzysztof Kozlowski , Magnus Damm , Prabhakar Mahadev Lad , linux-pwm@vger.kernel.org, linux-renesas-soc@vger.kernel.org Subject: Re: [PATCH v2 1/8] dt-bindings: pwm: Document RZ/G3E GPT support Message-ID: <175751729205.73392.13919616703987453446.robh@kernel.org> References: <20250909091225.128658-1-biju.das.jz@bp.renesas.com> <20250909091225.128658-2-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20250909091225.128658-2-biju.das.jz@bp.renesas.com> On Tue, 09 Sep 2025 10:12:11 +0100, Biju wrote: > From: Biju Das > > Document support for the GPT found on the Renesas RZ/G3E (R9A09G047) > SoC. > > The GPT is a 32-bit timer with 16 hardware channels (GPT0: 8 channel > and GPT1: 8channels). The hardware supports simultaneous control of > all channels. PWM waveforms can be generated by controlling the > up-counter, downcounter, or up- and down-counter. > > Signed-off-by: Biju Das > --- > v1->v2: > * Created separate document for RZ/G3E GPT. > * Updated commit header and description. > --- > .../bindings/pwm/renesas,rzg3e-gpt.yaml | 323 ++++++++++++++++++ > 1 file changed, 323 insertions(+) > create mode 100644 Documentation/devicetree/bindings/pwm/renesas,rzg3e-gpt.yaml > Reviewed-by: Rob Herring (Arm)