From: Will Deacon <will@kernel.org>
To: Shuai Xue <xueshuai@linux.alibaba.com>,
Jing Zhang <renyu.zj@linux.alibaba.com>,
Jonathan Corbet <corbet@lwn.net>,
Mark Rutland <mark.rutland@arm.com>,
Ilkka Koskinen <ilkka@os.amperecomputing.com>
Cc: catalin.marinas@arm.com, kernel-team@android.com,
Will Deacon <will@kernel.org>,
linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-perf-users@vger.kernel.org
Subject: Re: [PATCH] perf/dwc_pcie: Support counting multiple lane events in parallel
Date: Thu, 18 Sep 2025 17:43:07 +0100 [thread overview]
Message-ID: <175819993397.3464193.5312337667087987176.b4-ty@kernel.org> (raw)
In-Reply-To: <20250828223519.2812844-1-ilkka@os.amperecomputing.com>
On Thu, 28 Aug 2025 15:35:19 -0700, Ilkka Koskinen wrote:
> While Designware PCIe PMU allows to count only one time based event
> at a time, it allows to count all the lane events simultaneously.
> After the patch one is able to count a group of lane events:
>
> $ perf stat -e '{dwc_rootport/tx_memory_write,lane=1/,dwc_rootport/rx_memory_read,lane=0/}' dd if=/dev/nvme0n1 of=/dev/null bs=1M count=1
>
> Earlier the events wouldn't have been counted successfully.
>
> [...]
Applied to will (for-next/perf), thanks!
[1/1] perf/dwc_pcie: Support counting multiple lane events in parallel
https://git.kernel.org/will/c/71396cfac97d
Cheers,
--
Will
https://fixes.arm64.dev
https://next.arm64.dev
https://will.arm64.dev
prev parent reply other threads:[~2025-09-18 16:43 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-08-28 22:35 Ilkka Koskinen
2025-09-18 16:43 ` Will Deacon [this message]
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