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From: "Rob Herring (Arm)" <robh@kernel.org>
To: Claudiu <claudiu.beznea@tuxon.dev>
Cc: magnus.damm@gmail.com, mani@kernel.org, geert+renesas@glider.be,
	linux-renesas-soc@vger.kernel.org, conor+dt@kernel.org,
	devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
	Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>,
	kwilczynski@kernel.org, lpieralisi@kernel.org,
	linux-pci@vger.kernel.org, bhelgaas@google.com,
	p.zabel@pengutronix.de, krzk+dt@kernel.org
Subject: Re: [PATCH v6 1/6] dt-bindings: PCI: renesas,r9a08g045s33-pcie: Add Renesas RZ/G3S
Date: Thu, 30 Oct 2025 12:59:52 -0500	[thread overview]
Message-ID: <176184719160.107873.6758057982027005813.robh@kernel.org> (raw)
In-Reply-To: <20251029133653.2437024-2-claudiu.beznea.uj@bp.renesas.com>


On Wed, 29 Oct 2025 15:36:48 +0200, Claudiu wrote:
> From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
> 
> The PCIe IP available on the Renesas RZ/G3S complies with the PCI Express
> Base Specification 4.0. It is designed for root complex applications and
> features a single-lane (x1) implementation. Add documentation for it.
> 
> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
> ---
> 
> Changes in v6:
> - updated the patch title
> - described the functionalites that system controller has for PCIe
> - dropped /schemas/pci/pci-device.yaml# from allOf section
> - dropped max-link-speed from example
> - dropped pcie_port0 label from example
> 
> Changes in v5:
> - dropped Tb tag
> - style updates to the dma-ranges and ranges properties from
>   examples section
> - re-enabled the node from examples section
> 
> Changes in v4:
> - dropped "s33" string from compatible name
> - added port node documentation; due to this dropped Rob's Rb tag
> - reorderded properties
> - dropped spaces b/w "INT" and "A", "B", "C", "D" in comments
> 
> Changes in v3:
> - collected tags
> - updated the flags of ranges property from example
> 
> Changes in v2:
> - update the interrupt names by dropping "int" and "rc" string; due
>   to this the patch description was adjusted
> - added "interrupt-controller" and made it mandatory
> - s/clkl1pm/pm/g
> - dropped the legacy-interrupt-controller node; with this the gic
>   interrupt controller node was dropped as well as it is not needed
>   anymore
> - updated interrupt-map in example and added interrupt-controller
> - added clock-names as required property as the pm clock is not
>   handled though PM domains; this will allow the driver to have
>   the option to request the pm clock by its name when implementation
>   will be adjusted to used the pm clock
> - adjusted the size of dma-ranges to reflect the usage on
>   SMARC module board
> - moved "renesas,sysc" at the end of the node in example to align
>   with dts coding style
> 
>  .../bindings/pci/renesas,r9a08g045-pcie.yaml  | 249 ++++++++++++++++++
>  1 file changed, 249 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/pci/renesas,r9a08g045-pcie.yaml
> 

Reviewed-by: Rob Herring (Arm) <robh@kernel.org>


  reply	other threads:[~2025-10-30 17:59 UTC|newest]

Thread overview: 10+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-10-29 13:36 [PATCH v6 0/6] PCI: rzg3s-host: Add PCIe driver for Renesas RZ/G3S SoC Claudiu
2025-10-29 13:36 ` [PATCH v6 1/6] dt-bindings: PCI: renesas,r9a08g045s33-pcie: Add Renesas RZ/G3S Claudiu
2025-10-30 17:59   ` Rob Herring (Arm) [this message]
2025-10-29 13:36 ` [PATCH v6 2/6] PCI: rzg3s-host: Add Renesas RZ/G3S SoC host driver Claudiu
2025-11-13 15:24   ` Claudiu Beznea
2025-10-29 13:36 ` [PATCH v6 3/6] arm64: dts: renesas: r9a08g045: Add PCIe node Claudiu
2025-10-29 13:36 ` [PATCH v6 4/6] arm64: dts: renesas: rzg3s-smarc-som: Add PCIe reference clock Claudiu
2025-10-29 13:36 ` [PATCH v6 5/6] arm64: dts: renesas: rzg3s-smarc: Enable PCIe Claudiu
2025-10-29 13:36 ` [PATCH v6 6/6] arm64: defconfig: Enable PCIe for the Renesas RZ/G3S SoC Claudiu
2025-11-14 17:19 ` [PATCH v6 0/6] PCI: rzg3s-host: Add PCIe driver for " Manivannan Sadhasivam

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