Re: (subset) [PATCH v3 0/3] spi-cadence: support transmission with bits_per_word of 16 and 32

[Mark Brown <broonie@kernel.org>]

On Fri, 31 Oct 2025 15:30:00 +0800, Jun Guo wrote:
> The Cadence SPI IP supports configurable FIFO data widths during
> integration. On some SoCs, the FIFO data width is designed to be 16 or
> 32 bits at the chip design stage. However, the current driver only
> supports communication with an 8-bit FIFO data width. Therefore, these
> patches are added to enable the driver to support communication with
> 16-bit and 32-bit FIFO data widths.
> 
> [...]

Applied to

   https://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi.git for-next

Thanks!

[1/3] dt-bindings: spi: spi-cadence: update DT binding docs to support cix sky1 SoC
      commit: 55b5d192bab5e152bda8f8cefe837c4ed0ec60c5
[2/3] spi: spi-cadence: supports transmission with bits_per_word of 16 and 32
      commit: 4e00135b2dd1d7924a58bffa551b6ceb3bd836f2

All being well this means that it will be integrated into the linux-next
tree (usually sometime in the next 24 hours) and sent to Linus during
the next merge window (or sooner if it is a bug fix), however if
problems are discovered then the patch may be dropped or reverted.

You may get further e-mails resulting from automated or manual testing
and review of the tree, please engage with people reporting problems and
send followup patches addressing any issues that are reported if needed.

If any updates are required or you are submitting further changes they
should be sent as incremental updates against current git, existing
patches will not be replaced.

Please add any relevant lists and maintainers to the CCs when replying
to this mail.

Thanks,
Mark