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Mon, 17 Nov 2025 17:19:46 -0800 (PST) From: Inochi Amaoto To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen Wang , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Zixian Zeng Cc: Inochi Amaoto , devicetree@vger.kernel.org, sophgo@lists.linux.dev, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Han Gao , Longbin Li Subject: Re: [PATCH v2 0/4] Add SPI NOR DTS node for SG2042 SoC and boards using it Date: Tue, 18 Nov 2025 09:19:12 +0800 Message-ID: <176342869620.638242.11529006624321296909.b4-ty@gmail.com> X-Mailer: git-send-email 2.51.2 In-Reply-To: <20250916-sfg-spidts-v2-0-b5d9024fe1c8@gmail.com> References: <20250916-sfg-spidts-v2-0-b5d9024fe1c8@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 8bit On Tue, 16 Sep 2025 21:22:49 +0800, Zixian Zeng wrote: > [PATCH 1/4] and [PATCH 2/4] are copied from patch set [1] > [PATCH v4 4/4] with content changes: > > According to SG2042 Pioneer and SG2042_EVB_V1/V2 schematics, SPI-NOR Flash > cannot support QSPI due to hardware design. > Thus spi-(tx|rx)-bus-width must be set to 1. > > [...] Applied to dt/riscv, thanks! [1/4] riscv: dts: sophgo: Add SPI NOR node for SG2042 https://github.com/sophgo/linux/commit/59dc89fdfe0bbcce186116651bd017cfb9f70fc0 [2/4] riscv: dts: sophgo: Enable SPI NOR node for PioneerBox https://github.com/sophgo/linux/commit/f49314cbbc98f9ab2bf4eb82ccacbf79f179db6c [3/4] riscv: dts: sophgo: Enable SPI NOR node for SG2042_EVB_V1 https://github.com/sophgo/linux/commit/11f4d84c9f724ec4c6810567d6b9713b054bb28b [4/4] riscv: dts: sophgo: Enable SPI NOR node for SG2042_EVB_V2 https://github.com/sophgo/linux/commit/af5eb17ff893bf6e52680a31059e1816749c2d20 Thanks, Inochi