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Thu, 20 Nov 2025 05:13:01 -0800 From: Tariq Toukan To: Eric Dumazet , Jakub Kicinski , Paolo Abeni , Andrew Lunn , "David S. Miller" CC: Donald Hunter , Jiri Pirko , Jonathan Corbet , Saeed Mahameed , "Leon Romanovsky" , Tariq Toukan , Mark Bloch , , , , , Gal Pressman , Moshe Shemesh , Carolina Jubran , Cosmin Ratiu , Jiri Pirko Subject: [PATCH net-next 00/14] devlink and mlx5: Support cross-function rate scheduling Date: Thu, 20 Nov 2025 15:09:12 +0200 Message-ID: <1763644166-1250608-1-git-send-email-tariqt@nvidia.com> X-Mailer: git-send-email 2.8.0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF00026367:EE_|PH7PR12MB5928:EE_ X-MS-Office365-Filtering-Correlation-Id: 00ed1fbb-ad1a-4678-6b0b-08de283695b4 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|7416014|376014|36860700013|82310400026|30052699003|1800799024|13003099007; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?cl9vhuWhhoDEfj/gTFMer9FLMayEFSonHyqNe2j4ZsVjKajHRrhBVYwxf89Y?= =?us-ascii?Q?RzZZEUzlwe1RuBzP4C3szvTzu4zM25NnyUyXX0fM4ccrwMI1UiJEqOGLuoLW?= =?us-ascii?Q?lh87cDmVseYWxP8iN7Bhru9hLEdSg0pKMl7c9yfzt+14ya26norK8QWCfJDS?= =?us-ascii?Q?zciU0bl7w56X8liwABcqa36Mnm+62GVBtd/lLdFdOUZBEzvNnvf/81jJvDsz?= =?us-ascii?Q?buskAiY2kFLcIKrnu044yvc/yPZCT/DL75aDaXtaduqNsDyRMdh97CA79lgP?= =?us-ascii?Q?DgfriVvT4c5g6AX/DxXkG/4GJXVik76MSLoSrGdmluYxqVdUeIvVdvxZe1ei?= =?us-ascii?Q?GVDzMXtb8KRRgFDhx2Tlba9c/WHT0RhGGJgbO/QZ2kRhXuUuSpvRJzttr906?= =?us-ascii?Q?ZWJ/FPz9c2GelLnu5lLWABBAf0qemy1Aek5CYPpwjCZUMsgoqr170yDl3px1?= =?us-ascii?Q?qthsrCaOEMHavYeS8qcckfjUt5VORiRFFMLbHmbUOzZjMj2jmOHmQgafC4NT?= =?us-ascii?Q?R+9RequOv8M01SpuRjzg26ZQXJX59E3hRfM1syMp1WUxz9NUkrN4NspM+gWt?= =?us-ascii?Q?Ztm2tCo4DXAvHhaHBKV5qw5q9zRV+h7F5zyrLSoRlKh9YvlKgLj3R2jiMaRO?= =?us-ascii?Q?taJX9PmwqhyuUTjt+73LIf8ldpiVOghDj4cVBejuupNXiayJL2zki1BLHTmv?= =?us-ascii?Q?hbiGUNM70SW8ssxG/cu0pj3E0r2MXgP7vIEiQ47yJLZW3jEJCN9S+IQHCwwN?= =?us-ascii?Q?bQkprc0YpcrhVu5Y+lgcp5lYf2JPCqD0zLzS3YkMT46MXZbUn7yR8iImCtaE?= =?us-ascii?Q?4n8RhjMsgOf7dHVixBoOkkcBZUrm+ODboxqW6RdPO8XjDMUvhZvcMzy0ddzn?= =?us-ascii?Q?aWB24zpv0PuaVItodHqflBYqjiqEWLbOSl6L02tAlLS8hFAiJ/YCCayvB84o?= =?us-ascii?Q?PTGyS9MuofuHFsEck8zpxpgZWEtgjhLg4VnkV8DgwvWlyf+Ta8NsfNI0QYgB?= =?us-ascii?Q?2mn7D1ZtLb2eBEjCzfoC9fT0L3ZN1FNBJUBIXm1roQltdJGALEiutLqkUe90?= =?us-ascii?Q?cf4oN4HDh5lwETboH8CPnxfY1X5OZ715EnFVOkNupuEwf465rEoWjFg8aEQW?= =?us-ascii?Q?U5meH/t0O9oKmrDe9giHoHp+fpGcVuJTyZOOAZ9k6pucDhSruzEU+iz7W4AQ?= =?us-ascii?Q?MR+/TcNQKMYqlRVmmFGj/zktqmVsbb/222bvEvCdigmeWk/7QOKkIuqik35y?= =?us-ascii?Q?BIIn/PObvcQwom86+LwNdOWn5go4e7FkgxTTJR3BSmavkiGCo7r/74JWgcEt?= =?us-ascii?Q?zPOPZ1dUhA/F441KelcwJqlGMq0mv1Tm3ZSiX0H/Ok2tW5j9hj6wOIq5BeFZ?= =?us-ascii?Q?a/shlD+ZWGJ0QqfFKdA3d1OH4BRBWL4wc7cDQGBs9ID+b374bkuVD6L1nfwj?= =?us-ascii?Q?Pg/cDwRhVwKVvENkL5Fp9cEOzBNDVXfT+SgmTVpB0UBtobjKmbARcGOJKsJZ?= =?us-ascii?Q?9Z209TeznHPUdsaTQYu/EJILJJsfkNoRkMThQ9jnvWzNf4/nZl2kNW8Vd/XM?= =?us-ascii?Q?1Fe02ly5KT4ReY84Low=3D?= X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(7416014)(376014)(36860700013)(82310400026)(30052699003)(1800799024)(13003099007);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Nov 2025 13:13:23.6962 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 00ed1fbb-ad1a-4678-6b0b-08de283695b4 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF00026367.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB5928 Hi, This series by Cosmin and Jiri adds support for cross-function rate scheduling in devlink and mlx5. This is a different approach for the series discussed in [2] earlier this year. See detailed feature description by Cosmin below [1]. Code dependency: This series should apply cleanly after the pulling of 'net-2025_11_19_05_03', specifically commit f94c1a114ac2 ("devlink: rate: Unset parent pointer in devl_rate_nodes_destroy"). Regards, Tariq [1] devlink objects support rate management for TX scheduling, which involves maintaining a tree of rate nodes that corresponds to TX schedulers in hardware. 'man devlink-rate' has the full details. The tree of rate nodes is maintained per devlink object, protected by the devlink lock. There exists hardware capable of instantiating TX scheduling trees spanning multiple functions of the same physical device (and thus devlink objects) and therefore the current API and locking scheme is insufficient. This patch series changes the devlink rate implementation and API to allow supporting such hardware and managing TX scheduling trees across multiple functions of a physical device. Modeling this requires having devlink rate nodes with parents in other devlink objects. A naive approach that relies on the current one-lock-per-devlink model is impossible, as it would require in some cases acquiring multiple devlink locks in the correct order. The solution proposed in this patch series consists of two parts: 1. Modeling the underlying physical NIC as a shared devlink object on the faux bus and nesting all its PF devlink instances in it. 2. Changing the devlink rate implementation to store rates in this shared devlink object, if it exists, and use its lock to protect against concurrent changes of the scheduling tree. With these in place, cross-esw scheduling support is added to mlx5. The neat part about this approach is that it works for SFs as well, which are already nested in their parent PF instances. V1 of this patch series was sent a long time ago [2], using a different approach of storing rates in a shared rate domain with special locking rules. This new approach uses standard devlink instances and nesting. Patches: devlink rate changes for cross-device TX scheduling: devlink: Reverse locking order for nested instances documentation: networking: add shared devlink documentation devlink: Add helpers to lock nested-in instances devlink: Refactor devlink_rate_nodes_check devlink: Decouple rate storage from associated devlink object devlink: Add parent dev to devlink API devlink: Allow parent dev for rate-set and rate-new devlink: Allow rate node parents from other devlinks mlx5 support for cross-devuce TX scheduling: net/mlx5: Introduce shared devlink instance for PFs on same chip net/mlx5: Expose a function to clear a vport's parent net/mlx5: Store QoS sched nodes in the sh_devlink net/mlx5: qos: Support cross-esw tx scheduling net/mlx5: qos: Enable cross-device scheduling net/mlx5: Document devlink rates and cross-esw scheduling [2] https://lore.kernel.org/netdev/20250213180134.323929-1-tariqt@nvidia.com/ Cosmin Ratiu (12): devlink: Reverse locking order for nested instances devlink: Add helpers to lock nested-in instances devlink: Refactor devlink_rate_nodes_check devlink: Decouple rate storage from associated devlink object devlink: Add parent dev to devlink API devlink: Allow parent dev for rate-set and rate-new devlink: Allow rate node parents from other devlinks net/mlx5: Expose a function to clear a vport's parent net/mlx5: Store QoS sched nodes in the sh_devlink net/mlx5: qos: Support cross-device tx scheduling net/mlx5: qos: Enable cross-device scheduling net/mlx5: Document devlink rates Jiri Pirko (2): documentation: networking: add shared devlink documentation net/mlx5: Introduce shared devlink instance for PFs on same chip Documentation/netlink/specs/devlink.yaml | 22 +- .../networking/devlink/devlink-port.rst | 2 + .../networking/devlink/devlink-shared.rst | 66 ++++ Documentation/networking/devlink/index.rst | 3 + Documentation/networking/devlink/mlx5.rst | 33 ++ .../net/ethernet/mellanox/mlx5/core/Makefile | 5 +- .../net/ethernet/mellanox/mlx5/core/devlink.c | 1 + .../mellanox/mlx5/core/esw/devlink_port.c | 2 +- .../net/ethernet/mellanox/mlx5/core/esw/qos.c | 324 ++++++++---------- .../net/ethernet/mellanox/mlx5/core/esw/qos.h | 3 - .../net/ethernet/mellanox/mlx5/core/eswitch.c | 9 +- .../net/ethernet/mellanox/mlx5/core/eswitch.h | 14 +- .../net/ethernet/mellanox/mlx5/core/main.c | 18 + .../ethernet/mellanox/mlx5/core/sh_devlink.c | 183 ++++++++++ .../ethernet/mellanox/mlx5/core/sh_devlink.h | 16 + include/linux/mlx5/driver.h | 5 + include/net/devlink.h | 7 + include/uapi/linux/devlink.h | 2 + net/devlink/core.c | 48 ++- net/devlink/dev.c | 7 +- net/devlink/devl_internal.h | 11 +- net/devlink/netlink.c | 67 +++- net/devlink/netlink_gen.c | 23 +- net/devlink/netlink_gen.h | 8 + net/devlink/rate.c | 287 ++++++++++++---- 25 files changed, 873 insertions(+), 293 deletions(-) create mode 100644 Documentation/networking/devlink/devlink-shared.rst create mode 100644 drivers/net/ethernet/mellanox/mlx5/core/sh_devlink.c create mode 100644 drivers/net/ethernet/mellanox/mlx5/core/sh_devlink.h -- 2.31.1