From: Vinod Koul <vkoul@kernel.org>
To: Kishon Vijay Abraham I <kishon@kernel.org>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Qiang Yu <qiang.yu@oss.qualcomm.com>
Cc: linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
Prudhvi Yarlagadda <quic_pyarlaga@quicinc.com>,
Wenbin Yao <wenbin.yao@oss.qualcomm.com>,
Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>,
Manivannan Sadhasivam <mani@kernel.org>
Subject: Re: [PATCH v6 0/3] Add support for Glymur PCIe Gen5 x4
Date: Thu, 20 Nov 2025 22:41:50 +0530 [thread overview]
Message-ID: <176365871069.207696.4414338394387114477.b4-ty@kernel.org> (raw)
In-Reply-To: <20251103-glymur-pcie-upstream-v6-0-18a5e0a538dc@oss.qualcomm.com>
On Mon, 03 Nov 2025 23:56:23 -0800, Qiang Yu wrote:
> Glymur is the next generation compute SoC of Qualcomm. This patch series
> aims to add support for the fourth, fifth and sixth PCIe instance on it.
> The fifth PCIe instance on Glymur has a Gen5 4-lane PHY and fourth, fifth
> and sixth PCIe instance have a Gen5 2-lane PHY.
>
> The device tree changes and whatever driver patches that are not part of
> this patch series will be posted separately after official announcement of
> the SOC.
>
> [...]
Applied, thanks!
[1/3] dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: Document the Glymur QMP PCIe PHY
commit: d877f881cec508a46f76dbed7c46ab78bc1c0d87
[2/3] phy: qcom-qmp: pcs: Add v8.50 register offsets
commit: bc2ba6e3fb8a35cd83813be1bd4c5f066a401d8b
[3/3] phy: qcom: qmp-pcie: Add support for Glymur PCIe Gen5x4 PHY
commit: 1797c6677ad6298ca463b6ee42245e19e9cc1206
Best regards,
--
~Vinod
prev parent reply other threads:[~2025-11-20 17:11 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-11-04 7:56 Qiang Yu
2025-11-04 7:56 ` [PATCH v6 1/3] dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: Document the Glymur QMP PCIe PHY Qiang Yu
2025-11-04 7:56 ` [PATCH v6 2/3] phy: qcom-qmp: pcs: Add v8.50 register offsets Qiang Yu
2025-11-04 7:56 ` [PATCH v6 3/3] phy: qcom: qmp-pcie: Add support for Glymur PCIe Gen5x4 PHY Qiang Yu
2025-11-18 7:27 ` [PATCH v6 0/3] Add support for Glymur PCIe Gen5 x4 Qiang Yu
2025-11-18 17:10 ` Vinod Koul
2025-11-20 10:46 ` Qiang Yu
2025-11-20 11:20 ` Manivannan Sadhasivam
2025-11-21 9:11 ` Qiang Yu
2025-11-20 17:11 ` Vinod Koul [this message]
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