From: "tip-bot2 for Thomas Gleixner" <tip-bot2@linutronix.de>
To: linux-tip-commits@vger.kernel.org
Cc: Thomas Gleixner <tglx@linutronix.de>,
x86@kernel.org, linux-kernel@vger.kernel.org
Subject: [tip: x86/irq] x86/irq_remapping: Sanitize posted_msi_supported()
Date: Wed, 17 Dec 2025 17:48:29 -0000 [thread overview]
Message-ID: <176599370992.510.9601800206559033707.tip-bot2@tip-bot2> (raw)
In-Reply-To: <20251125214631.170499997@linutronix.de>
The following commit has been merged into the x86/irq branch of tip:
Commit-ID: 64d4c88270cf90089434e3db67ed443fd982a9a2
Gitweb: https://git.kernel.org/tip/64d4c88270cf90089434e3db67ed443fd982a9a2
Author: Thomas Gleixner <tglx@linutronix.de>
AuthorDate: Tue, 25 Nov 2025 22:50:49 +01:00
Committer: Thomas Gleixner <tglx@linutronix.de>
CommitterDate: Wed, 17 Dec 2025 18:44:17 +01:00
x86/irq_remapping: Sanitize posted_msi_supported()
posted_msi_supported() is a misnomer as it actually checks whether it is
enabled or not. Aside of that this does not take CONFIG_X86_POSTED_MSI into
account which is required to actually use it.
Rename it to posted_msi_enabled() and make the return value depend on
CONFIG_X86_POSTED_MSI, which allows the compiler to eliminate the related
dead code and data if disabled:
text data bss dec hex filename
10046 701 3296 14043 36db drivers/iommu/intel/irq_remapping.o
9904 413 3296 13613 352d drivers/iommu/intel/irq_remapping.o
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Link: https://patch.msgid.link/20251125214631.170499997@linutronix.de
---
arch/x86/include/asm/irq_remapping.h | 5 +++--
drivers/iommu/intel/irq_remapping.c | 4 ++--
2 files changed, 5 insertions(+), 4 deletions(-)
diff --git a/arch/x86/include/asm/irq_remapping.h b/arch/x86/include/asm/irq_remapping.h
index 4e55d17..37b94f4 100644
--- a/arch/x86/include/asm/irq_remapping.h
+++ b/arch/x86/include/asm/irq_remapping.h
@@ -67,9 +67,10 @@ static inline struct irq_domain *arch_get_ir_parent_domain(void)
extern bool enable_posted_msi;
-static inline bool posted_msi_supported(void)
+static inline bool posted_msi_enabled(void)
{
- return enable_posted_msi && irq_remapping_cap(IRQ_POSTING_CAP);
+ return IS_ENABLED(CONFIG_X86_POSTED_MSI) &&
+ enable_posted_msi && irq_remapping_cap(IRQ_POSTING_CAP);
}
#else /* CONFIG_IRQ_REMAP */
diff --git a/drivers/iommu/intel/irq_remapping.c b/drivers/iommu/intel/irq_remapping.c
index 8bcbfe3..ecb591e 100644
--- a/drivers/iommu/intel/irq_remapping.c
+++ b/drivers/iommu/intel/irq_remapping.c
@@ -1368,7 +1368,7 @@ static void intel_irq_remapping_prepare_irte(struct intel_ir_data *data,
break;
case X86_IRQ_ALLOC_TYPE_PCI_MSI:
case X86_IRQ_ALLOC_TYPE_PCI_MSIX:
- if (posted_msi_supported()) {
+ if (posted_msi_enabled()) {
prepare_irte_posted(irte);
data->irq_2_iommu.posted_msi = 1;
}
@@ -1460,7 +1460,7 @@ static int intel_irq_remapping_alloc(struct irq_domain *domain,
irq_data->hwirq = (index << 16) + i;
irq_data->chip_data = ird;
- if (posted_msi_supported() &&
+ if (posted_msi_enabled() &&
((info->type == X86_IRQ_ALLOC_TYPE_PCI_MSI) ||
(info->type == X86_IRQ_ALLOC_TYPE_PCI_MSIX)))
irq_data->chip = &intel_ir_chip_post_msi;
next prev parent reply other threads:[~2025-12-17 17:48 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-11-25 21:50 [patch V2 0/3] x86/irq: Bugfix and cleanup for posted MSI interrupts Thomas Gleixner
2025-11-25 21:50 ` [patch V2 1/3] x86/msi: Make irq_retrigger() functional for posted MSI Thomas Gleixner
2025-12-17 17:48 ` [tip: x86/urgent] " tip-bot2 for Thomas Gleixner
2025-11-25 21:50 ` [patch V2 2/3] x86/irq: Cleanup posted MSI code Thomas Gleixner
2025-12-17 17:48 ` [tip: x86/irq] " tip-bot2 for Thomas Gleixner
2025-12-18 22:03 ` tip-bot2 for Thomas Gleixner
2025-11-25 21:50 ` [patch V2 3/3] x86/irq_remapping: Sanitize posted_msi_supported() Thomas Gleixner
2025-12-17 17:48 ` tip-bot2 for Thomas Gleixner [this message]
2025-12-18 22:03 ` [tip: x86/irq] " tip-bot2 for Thomas Gleixner
2025-12-17 17:03 ` [patch V2 0/3] x86/irq: Bugfix and cleanup for posted MSI interrupts Luigi Rizzo
2025-12-17 17:37 ` Thomas Gleixner
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