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Tue, 23 Dec 2025 04:35:15 -0800 (PST) Received: from [192.168.1.102] ([120.60.139.28]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2a2f3d4cbe5sm128637585ad.60.2025.12.23.04.35.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 23 Dec 2025 04:35:15 -0800 (PST) From: Manivannan Sadhasivam X-Google-Original-From: Manivannan Sadhasivam To: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, bhelgaas@google.com, frank.li@nxp.com, l.stach@pengutronix.de, lpieralisi@kernel.org, kwilczynski@kernel.org, shawnguo@kernel.org, s.hauer@pengutronix.de, kernel@pengutronix.de, festevam@gmail.com, Richard Zhu Cc: linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, imx@lists.linux.dev, linux-kernel@vger.kernel.org In-Reply-To: <20251211064821.2707001-1-hongxing.zhu@nxp.com> References: <20251211064821.2707001-1-hongxing.zhu@nxp.com> Subject: Re: (subset) [PATCH v10 0/4] PCI: imx6: Add external reference clock mode support Message-Id: <176649331066.523506.9443864112044699350.b4-ty@kernel.org> Date: Tue, 23 Dec 2025 18:05:10 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit X-Mailer: b4 0.14.3 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMjIzMDEwMiBTYWx0ZWRfXxBNoJOijh8VO GS7ON1i9ZV16n2q9EFuiYTio01vxF+jxj0cJzGU0lUViwrnvoLoLOaqHVYGu/zsfS1ODj5Xuka8 UhX6TIqnhKE1YC4FBJ4jNPNLZJSn6kKBPCtehUVWE7oZ5B2b2B+VZvL0tvtzdnZxsu+hRD673LC V9yeKpTtyX8iY9xD+wEQ42ma2Oak+A0B4mFmHfXjahdb3ADT1cT+7kPKXLTg0CQ3qYoW+V5z3b3 9nKR2nk/5GAO1dDduJGiS25qK0V9qilTJAWMTrIwdUW56Sma0JUeb6k0f3+7lfQYdPie6YnsUkJ e/2N0v6xOKLl28rV1FOk0NTmYY3+K1bxzlcZRq7nTuHZAAVZMHFBgWqVgGW4tBjmGsfkzHZSddz tYP712HFczxH8SPTBM4qQhKxXkMObxO+DNmEH+vguXIT/dWRenWspF6U2jZEar8eTG5ofWgfHDj LGPGS839QeiLxybblUg== X-Authority-Analysis: v=2.4 cv=Zb0Q98VA c=1 sm=1 tr=0 ts=694a8c84 cx=c_pps a=JL+w9abYAAE89/QcEU+0QA==:117 a=wbxd9xFQoh2bOL7BUxlcyw==:17 a=IkcTkHD0fZMA:10 a=wP3pNCr1ah4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=VwQbUJbxAAAA:8 a=EXx6v-oOm7wFthy7ysMA:9 a=QEXdDO2ut3YA:10 a=324X-CrmTo6CU4MGRt3R:22 X-Proofpoint-ORIG-GUID: nmu1mByNe2Iqs6CQtpLVj7UbImV9yPb8 X-Proofpoint-GUID: nmu1mByNe2Iqs6CQtpLVj7UbImV9yPb8 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-12-23_03,2025-12-22_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 priorityscore=1501 malwarescore=0 impostorscore=0 phishscore=0 spamscore=0 bulkscore=0 adultscore=0 suspectscore=0 clxscore=1015 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2512120000 definitions=main-2512230102 On Thu, 11 Dec 2025 14:48:17 +0800, Richard Zhu wrote: > I'm really sorry to send this version patch-set late, because that I was > engaged in other emergent tasks in the past weeks. And didn't have time > to continue this topic. Now, I have chance to continue doing this again. > Sorry to bring the inconvenience to the patch review. > > i.MX95 PCIes have two reference clock inputs: one from internal PLL. > It's wired inside chip and present as "ref" clock. It's not an optional > clock. The other from off chip crystal oscillator. The "extref" clock > refers to a reference clock from an external crystal oscillator through > the CLKIN_N/P pair PADs. It is an optional clock, relied on the board > design. > > [...] Applied, thanks! [1/4] dt-bindings: PCI: dwc: Add external reference clock input commit: 418970983059aa06302ddd5ca76d441973b537c1 [2/4] dt-bindings: PCI: pci-imx6: Add external reference clock input commit: 1352f58d7c8dfb6ba0fbd2041bfc8b4b3966ec67 [3/4] PCI: imx6: Add external reference clock input mode support commit: d8574ce57d760a958623c8f6bc3c55b5187a7bd7 Best regards, -- Manivannan Sadhasivam