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Tue, 23 Dec 2025 07:58:33 -0800 (PST) Received: from [192.168.1.102] ([120.56.200.112]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2a2f3d7754asm131271795ad.100.2025.12.23.07.58.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 23 Dec 2025 07:58:33 -0800 (PST) From: Manivannan Sadhasivam X-Google-Original-From: Manivannan Sadhasivam To: Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Joel Stanley , Andrew Jeffery , Bjorn Helgaas , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Linus Walleij , Philipp Zabel , Neil Armstrong , Jacky Chou Cc: linux-aspeed@lists.ozlabs.org, linux-pci@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Andrew Jeffery , openbmc@lists.ozlabs.org, linux-gpio@vger.kernel.org In-Reply-To: <20251216-upstream_pcie_rc-v7-0-4aeb0f53c4ce@aspeedtech.com> References: <20251216-upstream_pcie_rc-v7-0-4aeb0f53c4ce@aspeedtech.com> Subject: Re: (subset) [PATCH v7 0/7] Add ASPEED PCIe Root Complex support Message-Id: <176650550798.2188958.10356654881464455126.b4-ty@kernel.org> Date: Tue, 23 Dec 2025 21:28:27 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit X-Mailer: b4 0.14.3 X-Proofpoint-ORIG-GUID: dZTXRAfo_NniMAIp70xrf02eqSzIP5lv X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMjIzMDEzMiBTYWx0ZWRfX+Qua0TTaKdGQ tG+lYzh4IMorEM7s7CUNZZJZmaXAqYNOJ/U1ECaOMF9OmhG7v3+f3zYiCgeqHQ6PnT0TZhcNlrt 1CgxLfpC3OYG6fNlQS4/276XZG1jSuk45iQnt6zfo85FPKkg3AaiPASNAbEF+RN5jFLtpuBbhix Q6PZw/bLAu3Py4XXKI6rhm2ZUKR+evNGRObiX+XY+scCpepoiDhjl+iqjniwSaIEqaWZgE0sCHV quDPoNpQaFlme5EunU80WUDUUVf+VkX38Y/ZtrGm7NCo4yRHr6IHu/E3A9Fm7Y80i/Ara3bQ+ZX jJAMVe0C8ppFHRlKdx7vD2o2ZRBiF6IAE/ePi5g8odaUf5Hk+fRBNU9S2wDen/HmSsU3Hp22nUN F0CM1/WSyGceSwho1BIS3mDMd4wqVakOukqYjX4AHC7VGjSumWIr83VEviFHqbhtRFG714D06KV AeUUMjKfvHTrXrkC5gw== X-Proofpoint-GUID: dZTXRAfo_NniMAIp70xrf02eqSzIP5lv X-Authority-Analysis: v=2.4 cv=NZDrFmD4 c=1 sm=1 tr=0 ts=694abc2b cx=c_pps a=JL+w9abYAAE89/QcEU+0QA==:117 a=31AEnvkI3DvSdtIumApubw==:17 a=IkcTkHD0fZMA:10 a=wP3pNCr1ah4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=VwQbUJbxAAAA:8 a=oUgZFhhkZxxgqap4hUAA:9 a=QEXdDO2ut3YA:10 a=324X-CrmTo6CU4MGRt3R:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-12-23_03,2025-12-22_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 spamscore=0 clxscore=1015 impostorscore=0 malwarescore=0 suspectscore=0 phishscore=0 bulkscore=0 adultscore=0 lowpriorityscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2512120000 definitions=main-2512230132 On Tue, 16 Dec 2025 09:49:59 +0800, Jacky Chou wrote: > This patch series adds support for the ASPEED PCIe Root Complex, > including device tree bindings, pinctrl support, and the PCIe host controller > driver. The patches introduce the necessary device tree nodes, pinmux groups, > and driver implementation to enable PCIe functionality on ASPEED platforms. > Currently, the ASPEED PCIe Root Complex only supports a single port. > > Summary of changes: > - Add device tree binding documents for ASPEED PCIe PHY and PCIe RC > - Update MAINTAINERS for new bindings and driver > - Implement ASPEED PCIe PHY driver > - Implement ASPEED PCIe Root Complex host controller driver > > [...] Applied, thanks! [2/7] dt-bindings: PCI: Add ASPEED PCIe RC support commit: a20df1a7683d6c1416c0f56fb737554b9abe9959 [5/7] PCI: Add FMT, TYPE and CPL status definition for TLP header commit: 73ce5ba701a53ad89c623a641401288844f526ac [6/7] PCI: aspeed: Add ASPEED PCIe RC driver commit: 9aa0cb68fcc16280c8c8bdd22dc770af8dd7349f [7/7] MAINTAINERS: Add ASPEED PCIe RC driver commit: e5c2061442dda716fb08cc4eff485220c94e6475 Best regards, -- Manivannan Sadhasivam