From: Vinod Koul <vkoul@kernel.org>
To: Neil Armstrong <neil.armstrong@linaro.org>,
Heiko Stuebner <heiko@sntech.de>,
Dmitry Baryshkov <lumag@kernel.org>,
Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
Cc: kernel@collabora.com, linux-phy@lists.infradead.org,
linux-arm-kernel@lists.infradead.org,
linux-rockchip@lists.infradead.org,
linux-kernel@vger.kernel.org,
Derek Foreman <derek.foreman@collabora.com>
Subject: Re: [PATCH v2 0/2] Fixup HDMI PLL for phy-rockchip-samsung-hdptx
Date: Tue, 23 Dec 2025 23:14:33 +0530 [thread overview]
Message-ID: <176651187342.759340.7650219710991415977.b4-ty@kernel.org> (raw)
In-Reply-To: <20251221-phy-hdptx-pll-fix-v2-0-ae4abf7f75a1@collabora.com>
On Sun, 21 Dec 2025 12:36:22 +0200, Cristian Ciocaltea wrote:
> The Samsung HDMI/eDP TX PHY is currently not able to provide an accurate
> enough PLL output frequency to match the TMDS rate of a 1080p@120Hz
> display mode, when used with 10 bpc RGB.
>
> This patch set adds a new entry to the TMDS configuration table,
> providing the necessary frequency division coefficients for the PHY PLL
> to generate the expected 461.101250 MHz output.
>
> [...]
Applied, thanks!
[1/2] phy: rockchip: samsung-hdptx: Pre-compute HDMI PLL config for 461.10125 MHz output
commit: f2daf0c67a1767ff6536aa3e96599afb42ca42e7
[2/2] phy: rockchip: samsung-hdptx: Cleanup TMDS PLL config table
commit: 3be8131ee936abb6ff56ca9ec9d38c911251410b
Best regards,
--
~Vinod
prev parent reply other threads:[~2025-12-23 17:44 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-12-21 10:36 Cristian Ciocaltea
2025-12-21 10:36 ` [PATCH v2 1/2] phy: rockchip: samsung-hdptx: Pre-compute HDMI PLL config for 461.10125 MHz output Cristian Ciocaltea
2025-12-21 10:36 ` [PATCH v2 2/2] phy: rockchip: samsung-hdptx: Cleanup TMDS PLL config table Cristian Ciocaltea
2025-12-23 17:44 ` Vinod Koul [this message]
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