From: Vinod Koul <vkoul@kernel.org>
To: jckuo@nvidia.com, kishon@kernel.org, thierry.reding@gmail.com,
jonathanh@nvidia.com, Wayne Chang <waynec@nvidia.com>
Cc: haotienh@nvidia.com, linux-phy@lists.infradead.org,
linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org,
stable@vger.kernel.org
Subject: Re: [PATCH 1/1] phy: tegra: xusb: Explicitly configure HS_DISCON_LEVEL to 0x7
Date: Wed, 24 Dec 2025 13:02:22 +0530 [thread overview]
Message-ID: <176656154202.817702.8391206381480779242.b4-ty@kernel.org> (raw)
In-Reply-To: <20251212032116.768307-1-waynec@nvidia.com>
On Fri, 12 Dec 2025 11:21:16 +0800, Wayne Chang wrote:
> The USB2 Bias Pad Control register manages analog parameters for signal
> detection. Previously, the HS_DISCON_LEVEL relied on hardware reset
> values, which may lead to the detection failure.
>
> Explicitly configure HS_DISCON_LEVEL to 0x7. This ensures the disconnect
> threshold is sufficient to guarantee reliable detection.
>
> [...]
Applied, thanks!
[1/1] phy: tegra: xusb: Explicitly configure HS_DISCON_LEVEL to 0x7
commit: b246caa68037aa495390a60d080acaeb84f45fff
Best regards,
--
~Vinod
prev parent reply other threads:[~2025-12-24 7:32 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-12-12 3:21 Wayne Chang
2025-12-24 7:32 ` Vinod Koul [this message]
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