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([2a01:e0a:90c:e290:4a89:8c32:4adc:fc67]) by smtp.gmail.com with ESMTPSA id j13sm1389076wrw.93.2021.04.30.01.35.10 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 30 Apr 2021 01:35:11 -0700 (PDT) Subject: Re: [PATCH v3 2/3] drm/bridge: nwl-dsi: Remove a check on unchanged HS clock rate from ->mode_set() To: Liu Ying , dri-devel@lists.freedesktop.org Cc: linux-kernel@vger.kernel.org, a.hajda@samsung.com, robert.foss@linaro.org, Laurent.pinchart@ideasonboard.com, jonas@kwiboo.se, jernej.skrabec@siol.net, airlied@linux.ie, daniel@ffwll.ch, agx@sigxcpu.org, robert.chiras@nxp.com, linux-imx@nxp.com References: <1619170003-4817-1-git-send-email-victor.liu@nxp.com> <1619170003-4817-3-git-send-email-victor.liu@nxp.com> From: Neil Armstrong Organization: Baylibre Message-ID: <176671b3-b0f8-d1be-79a1-ebf8ee9123e9@baylibre.com> Date: Fri, 30 Apr 2021 10:35:10 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.7.1 MIME-Version: 1.0 In-Reply-To: <1619170003-4817-3-git-send-email-victor.liu@nxp.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 23/04/2021 11:26, Liu Ying wrote: > The check on unchanged HS clock rate in ->mode_set() improves > the callback's performance a bit by early return. However, > the up-coming patch would get MIPI DSI controller and PHY ready > in ->mode_set() after that check, thus likely skipped. > So, this patch removes that check to make sure MIPI DSI controller > and PHY will be brought up and taken down from ->mode_set() and > ->atomic_disable() respectively in pairs. > > Cc: Andrzej Hajda > Cc: Neil Armstrong > Cc: Robert Foss > Cc: Laurent Pinchart > Cc: Jonas Karlman > Cc: Jernej Skrabec > Cc: David Airlie > Cc: Daniel Vetter > Cc: Guido Günther > Cc: Robert Chiras > Cc: NXP Linux Team > Signed-off-by: Liu Ying > --- > v2->v3: > * Split from the single patch in v2 to clarify changes. (Neil) > > drivers/gpu/drm/bridge/nwl-dsi.c | 7 ------- > 1 file changed, 7 deletions(-) > > diff --git a/drivers/gpu/drm/bridge/nwl-dsi.c b/drivers/gpu/drm/bridge/nwl-dsi.c > index c65ca860712d2..601ccc4a7cdc7 100644 > --- a/drivers/gpu/drm/bridge/nwl-dsi.c > +++ b/drivers/gpu/drm/bridge/nwl-dsi.c > @@ -856,13 +856,6 @@ nwl_dsi_bridge_mode_set(struct drm_bridge *bridge, > if (ret < 0) > return; > > - /* > - * If hs clock is unchanged, we're all good - all parameters are > - * derived from it atm. > - */ > - if (new_cfg.mipi_dphy.hs_clk_rate == dsi->phy_cfg.mipi_dphy.hs_clk_rate) > - return; > - > phy_ref_rate = clk_get_rate(dsi->phy_ref_clk); > DRM_DEV_DEBUG_DRIVER(dev, "PHY at ref rate: %lu\n", phy_ref_rate); > /* Save the new desired phy config */ > Reviewed-by: Neil Armstrong