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Sat, 27 Dec 2025 04:23:54 GMT Received: from smtpav06.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 0C1FD20040; Sat, 27 Dec 2025 04:23:54 +0000 (GMT) Received: from smtpav06.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id EEB9E20049; Sat, 27 Dec 2025 04:23:51 +0000 (GMT) Received: from Linuxdev.ibmuc.com (unknown [9.124.212.100]) by smtpav06.fra02v.mail.ibm.com (Postfix) with ESMTP; Sat, 27 Dec 2025 04:23:51 +0000 (GMT) From: Madhavan Srinivasan To: Michael Ellerman , Nicholas Piggin , "Christophe Leroy (CS GROUP)" Cc: linux-kernel@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, Christian Zigotzky , Guenter Roeck Subject: Re: [PATCH] powerpc/32: Restore disabling of interrupts at interrupt/syscall exit Date: Sat, 27 Dec 2025 09:53:50 +0530 Message-ID: <176680916371.22434.11687040747709449917.b4-ty@linux.ibm.com> X-Mailer: git-send-email 2.52.0 In-Reply-To: <585ea521b2be99d293b539bbfae148366cfb3687.1766146895.git.chleroy@kernel.org> References: <585ea521b2be99d293b539bbfae148366cfb3687.1766146895.git.chleroy@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 8bit X-TM-AS-GCONF: 00 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMjI3MDAzNSBTYWx0ZWRfX3ZZ7oNw/YdBq 2RyJ2zr9tPjcSIpKravsW/G78pcCDGclh9RGWLRMFVGp5YrfEgzLmZVT703CzJWsl9jO8l5E5QM 7Sz8KhRBvRyX79AOXCOwOtnS2YNxylPXfhndkfrDPZAJMUoTx9DgOwohdq3tLf+dBEVWd8z6Lvr t0VicTYG0vZ60xygQ0gkvInEqJetb7l1gneDPXiCurcc83uAr85AzOxtlYui6fgBjsGLar5oOlD 6JNkHecfDsC7xXnErf/239lTNwgqRQFnHtjUqYapMsNaxzjhKmFAlDtvvhprtMdRBIjh34NZxE2 HGPDTFqbFe4m4FswriUyK0Rlh0YM5/cGTb42VYams97AAD3s8F9r76vaztitTjOGrj7+ncki3DJ Au+Z3l9yBSgkrbuGM0oKfkF1ta5+zE/hX35VNJ36vnXQ29hcDG6EbgbB9heKVPXM1kWL/coNL1U kpgyBGS31ls8lpsIKKw== X-Proofpoint-GUID: BYOGtB0527OThtQgi6t_RM6hnw8fCLtV X-Authority-Analysis: v=2.4 cv=B4+0EetM c=1 sm=1 tr=0 ts=694f5f5d cx=c_pps a=3Bg1Hr4SwmMryq2xdFQyZA==:117 a=3Bg1Hr4SwmMryq2xdFQyZA==:17 a=IkcTkHD0fZMA:10 a=wP3pNCr1ah4A:10 a=VkNPw1HP01LnGYTKEx00:22 a=VwQbUJbxAAAA:8 a=grMsOQSJOuImfsIcpOsA:9 a=QEXdDO2ut3YA:10 X-Proofpoint-ORIG-GUID: JkCSQwrNWR5zJWR_auDj-ruIUnlqX9Rm X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-12-27_02,2025-12-26_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 adultscore=0 phishscore=0 bulkscore=0 clxscore=1015 malwarescore=0 impostorscore=0 spamscore=0 lowpriorityscore=0 priorityscore=1501 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2512120000 definitions=main-2512270035 On Fri, 19 Dec 2025 13:23:52 +0100, Christophe Leroy (CS GROUP) wrote: > Commit 2997876c4a1a ("powerpc/32: Restore clearing of MSR[RI] at > interrupt/syscall exit") delayed clearing of MSR[RI], but missed that > both MSR[RI] and MSR[EE] are cleared at the same time, so the commit > also delayed the disabling of interrupts, leading to unexpected > behaviour. > > To fix that, mostly revert the blamed commit and restore the clearing > of MSR[RI] in interrupt_exit_kernel_prepare() instead. For 8xx it > implies adding a synchronising instruction after the mtspr in order to > make sure no instruction counter interrupt (used for perf events) will > fire just after clearing MSR[RI]. > > [...] Applied to powerpc/fixes. [1/1] powerpc/32: Restore disabling of interrupts at interrupt/syscall exit https://git.kernel.org/powerpc/c/608328ba5b0619cbc28b409296b5e3840bcb97b6 cheers