From: Bjorn Andersson <andersson@kernel.org>
To: Konrad Dybcio <konradybcio@kernel.org>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Rajendra Nayak <quic_rjendra@quicinc.com>,
Sibi Sankar <sibi.sankar@oss.qualcomm.com>,
Abel Vesa <abelvesa@kernel.org>
Cc: Taniya Das <taniya.das@oss.qualcomm.com>,
Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>,
linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH RFC] arm64: dts: qcom: x1e80100: Fix USB combo PHYs SS1 and SS2 ref clocks
Date: Mon, 5 Jan 2026 08:07:09 -0600 [thread overview]
Message-ID: <176762206421.2923194.528670029626982446.b4-ty@kernel.org> (raw)
In-Reply-To: <20251103-dts-qcom-x1e80100-fix-combo-ref-clks-v1-1-f395ec3cb7e8@linaro.org>
On Mon, 03 Nov 2025 18:51:40 +0200, Abel Vesa wrote:
> It seems the USB combo SS1 and SS2 ref clocks have another gate, unlike
> the SS0. These gates are part of the TCSR clock controller.
>
> At least on Dell XPS 13 (9345), if the ref clock provided by the TCSR
> clock controller for SS1 PHY is disabled on the clk_disable_unused late
> initcall, the PHY fails to initialize. It doesn't happen on the SS0 PHY
> and the SS2 is not used on this device.
>
> [...]
Applied, thanks!
[1/1] arm64: dts: qcom: x1e80100: Fix USB combo PHYs SS1 and SS2 ref clocks
commit: 3af51501e2b8c87564b5cda43b0e5c316cf54717
Best regards,
--
Bjorn Andersson <andersson@kernel.org>
prev parent reply other threads:[~2026-01-05 14:07 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-11-03 16:51 Abel Vesa
2025-11-04 12:36 ` Konrad Dybcio
2025-11-05 11:47 ` Taniya Das
2025-11-07 10:29 ` Neil Armstrong
2026-01-05 14:07 ` Bjorn Andersson [this message]
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